summaryrefslogtreecommitdiffstats
path: root/target/avr
Commit message (Expand)AuthorAgeFilesLines
* target/avr: Fix interrupt executionIvanov Arkasha2021-03-151-1/+3
* target/avr: Fix some comment spelling errorsLichang Zhao2021-03-151-3/+3
* target/avr/cpu: Use device_class_set_parent_realize()Philippe Mathieu-Daudé2021-02-201-3/+1Star
* cpu: tcg_ops: move to tcg-cpu-ops.h, keep a pointer in CPUClassClaudio Fontana2021-02-052-7/+17
* cpu: move cc->do_interrupt to tcg_opsClaudio Fontana2021-02-052-3/+3
* cpu: Move tlb_fill to tcg_opsEduardo Habkost2021-02-051-1/+1
* cpu: Move cpu_exec_* to tcg_opsEduardo Habkost2021-02-051-1/+1
* cpu: Move synchronize_from_tb() to tcg_opsEduardo Habkost2021-02-051-1/+1
* cpu: Introduce TCGCpuOperations structEduardo Habkost2021-02-051-1/+1
* tcg: Make tb arg to synchronize_from_tb constRichard Henderson2021-01-071-1/+2
* migration: Replace migration's JSON writer by the general oneMarkus Armbruster2020-12-191-2/+2
* qom: Remove module_obj_name parameter from OBJECT_DECLARE* macrosEduardo Habkost2020-09-181-1/+1
* Use OBJECT_DECLARE_TYPE where possibleEduardo Habkost2020-09-091-4/+2Star
* Use DECLARE_*CHECKER* macrosEduardo Habkost2020-09-091-6/+2Star
* Move QOM typedefs and add missing includesEduardo Habkost2020-09-091-3/+5
* meson: targetPaolo Bonzini2020-08-214-36/+22Star
* meson: rename included C source files to .c.incPaolo Bonzini2020-08-213-4/+4
* target/avr/disas: Fix store instructions display orderPhilippe Mathieu-Daudé2020-07-111-10/+10
* target/avr/cpu: Fix $PC displayed addressPhilippe Mathieu-Daudé2020-07-111-1/+1
* target/avr/cpu: Drop tlb_flush() in avr_cpu_reset()Philippe Mathieu-Daudé2020-07-111-2/+0Star
* target/avr: Register AVR support with the rest of QEMUMichael Rolnik2020-07-111-0/+34
* target/avr: Add support for disassembling via option '-d in_asm'Michael Rolnik2020-07-114-1/+259
* target/avr: Initialize TCG register variablesMichael Rolnik2020-07-111-0/+29
* target/avr: Add instruction translation - CPU main translation functionMichael Rolnik2020-07-111-0/+213
* target/avr: Add instruction translation - MCU Control InstructionsMichael Rolnik2020-07-112-0/+73
* target/avr: Add instruction translation - Bit and Bit-test InstructionsMichael Rolnik2020-07-112-0/+261
* target/avr: Add instruction translation - Data Transfer InstructionsMichael Rolnik2020-07-112-0/+1046
* target/avr: Add instruction translation - Branch InstructionsMichael Rolnik2020-07-112-0/+576
* target/avr: Add instruction translation - Arithmetic and Logic InstructionsMichael Rolnik2020-07-112-0/+896
* target/avr: Add instruction translation - Register definitionsMichael Rolnik2020-07-111-0/+142
* target/avr: Add instruction helpersMichael Rolnik2020-07-112-0/+238
* target/avr: Add definitions of AVR core typesMichael Rolnik2020-07-101-0/+151
* target/avr: Introduce enumeration AVRFeatureMichael Rolnik2020-07-101-0/+46
* target/avr: CPU class: Add GDB supportMichael Rolnik2020-07-103-0/+90
* target/avr: CPU class: Add migration supportMichael Rolnik2020-07-103-0/+122
* target/avr: CPU class: Add memory management supportMichael Rolnik2020-07-102-0/+53
* target/avr: CPU class: Add interrupt handling supportMichael Rolnik2020-07-102-0/+91
* target/avr: Introduce basic CPU class objectMichael Rolnik2020-07-103-0/+399
* target/avr: Add basic parameters of the new platformMichael Rolnik2020-07-102-0/+102
generated by cgit v1.2.3-55-g7522 (git 2.39.0) at 2024-12-18 11:35:53 +0100