| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | target/i386: Always completely initialize TranslateFault | Richard Henderson | 2022-12-01 | 1 | -15/+19 |
| * | target/i386: allow MMX instructions with CR4.OSFXSR=0 | Paolo Bonzini | 2022-12-01 | 1 | -1/+2 |
| * | target/i386: hardcode R_EAX as destination register for LAHF/SAHF | Paolo Bonzini | 2022-11-15 | 1 | -2/+2 |
| * | target/i386: fix cmpxchg with 32-bit register destination | Paolo Bonzini | 2022-11-15 | 1 | -26/+56 |
| * | Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into staging | Stefan Hajnoczi | 2022-11-03 | 2 | -6/+6 |
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| | * | target/i386: Fix test for paging enabled | Richard Henderson | 2022-11-02 | 1 | -5/+5 |
| | * | target/i386: Fix calculation of LOCK NEG eflags | Qi Hu | 2022-10-31 | 1 | -1/+1 |
| * | | target/i386: Expand eflags updates inline | Richard Henderson | 2022-10-31 | 2 | -46/+25 |
| * | | accel/tcg: Remove will_exit argument from cpu_restore_state | Richard Henderson | 2022-10-31 | 1 | -1/+1 |
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| * | target/i386: Convert to tcg_ops restore_state_to_opc | Richard Henderson | 2022-10-26 | 2 | -15/+19 |
| * | target/i386: implement FMA instructions | Paolo Bonzini | 2022-10-22 | 4 | -0/+93 |
| * | target/i386: implement F16C instructions | Paolo Bonzini | 2022-10-20 | 3 | -1/+26 |
| * | target/i386: introduce function to set rounding mode from FPCW or MXCSR bits | Paolo Bonzini | 2022-10-20 | 1 | -39/+21 |
| * | target/i386: decode-new: avoid out-of-bounds access to xmm_regs[-1] | Paolo Bonzini | 2022-10-20 | 1 | -1/+1 |
| * | target/i386: remove old SSE decoder | Paolo Bonzini | 2022-10-18 | 3 | -1722/+19 |
| * | target/i386: move 3DNow to the new decoder | Paolo Bonzini | 2022-10-18 | 5 | -75/+74 |
| * | target/i386: implement VLDMXCSR/VSTMXCSR | Paolo Bonzini | 2022-10-18 | 2 | -0/+45 |
| * | target/i386: implement XSAVE and XRSTOR of AVX registers | Paolo Bonzini | 2022-10-18 | 1 | -3/+75 |
| * | target/i386: reimplement 0x0f 0x28-0x2f, add AVX | Paolo Bonzini | 2022-10-18 | 3 | -0/+185 |
| * | target/i386: reimplement 0x0f 0x10-0x17, add AVX | Paolo Bonzini | 2022-10-18 | 3 | -0/+254 |
| * | target/i386: reimplement 0x0f 0xc2, 0xc4-0xc6, add AVX | Paolo Bonzini | 2022-10-18 | 3 | -0/+81 |
| * | target/i386: reimplement 0x0f 0x38, add AVX | Paolo Bonzini | 2022-10-18 | 4 | -7/+318 |
| * | target/i386: Use tcg gvec ops for pmovmskb | Richard Henderson | 2022-10-18 | 1 | -5/+83 |
| * | target/i386: reimplement 0x0f 0x3a, add AVX | Paolo Bonzini | 2022-10-18 | 3 | -1/+386 |
| * | target/i386: reimplement 0x0f 0xd0-0xd7, 0xe0-0xe7, 0xf0-0xf7, add AVX | Paolo Bonzini | 2022-10-18 | 4 | -11/+122 |
| * | target/i386: reimplement 0x0f 0x70-0x77, add AVX | Paolo Bonzini | 2022-10-18 | 3 | -6/+293 |
| * | target/i386: reimplement 0x0f 0x78-0x7f, add AVX | Paolo Bonzini | 2022-10-18 | 3 | -0/+138 |
| * | target/i386: reimplement 0x0f 0x50-0x5f, add AVX | Paolo Bonzini | 2022-10-18 | 3 | -1/+210 |
| * | target/i386: reimplement 0x0f 0xd8-0xdf, 0xe8-0xef, 0xf8-0xff, add AVX | Paolo Bonzini | 2022-10-18 | 3 | -1/+63 |
| * | target/i386: reimplement 0x0f 0x60-0x6f, add AVX | Paolo Bonzini | 2022-10-18 | 3 | -1/+262 |
| * | target/i386: Introduce 256-bit vector helpers | Paolo Bonzini | 2022-10-18 | 1 | -0/+3 |
| * | target/i386: provide 3-operand versions of unary scalar helpers | Paolo Bonzini | 2022-10-18 | 1 | -9/+13 |
| * | target/i386: extend helpers to support VEX.V 3- and 4- operand encodings | Paolo Bonzini | 2022-10-18 | 1 | -57/+124 |
| * | target/i386: move scalar 0F 38 and 0F 3A instruction to new decoder | Paolo Bonzini | 2022-10-18 | 3 | -289/+321 |
| * | target/i386: validate SSE prefixes directly in the decoding table | Paolo Bonzini | 2022-10-18 | 2 | -0/+38 |
| * | target/i386: validate VEX prefixes via the instructions' exception classes | Paolo Bonzini | 2022-10-18 | 4 | -12/+239 |
| * | target/i386: add AVX_EN hflag | Paul Brook | 2022-10-18 | 1 | -0/+1 |
| * | target/i386: add CPUID feature checks to new decoder | Paolo Bonzini | 2022-10-18 | 2 | -0/+75 |
| * | target/i386: add CPUID[EAX=7,ECX=0].ECX to DisasContext | Paolo Bonzini | 2022-10-18 | 1 | -0/+2 |
| * | target/i386: add ALU load/writeback core | Paolo Bonzini | 2022-10-18 | 4 | -1/+212 |
| * | target/i386: add core of new i386 decoder | Paolo Bonzini | 2022-10-18 | 4 | -8/+1020 |
| * | target/i386: make rex_w available even in 32-bit mode | Paolo Bonzini | 2022-10-18 | 1 | -5/+5 |
| * | target/i386: make ldo/sto operations consistent with ldq | Paolo Bonzini | 2022-10-18 | 1 | -21/+22 |
| * | target/i386: Use probe_access_full for final stage2 translation | Richard Henderson | 2022-10-18 | 1 | -14/+28 |
| * | target/i386: Use atomic operations for pte updates | Richard Henderson | 2022-10-18 | 1 | -74/+168 |
| * | target/i386: Combine 5 sets of variables in mmu_translate | Richard Henderson | 2022-10-18 | 1 | -87/+91 |
| * | target/i386: Use MMU_NESTED_IDX for vmload/vmsave | Richard Henderson | 2022-10-18 | 2 | -136/+126 |
| * | target/i386: Add MMU_PHYS_IDX and MMU_NESTED_IDX | Richard Henderson | 2022-10-18 | 2 | -29/+56 |
| * | target/i386: Reorg GET_HPHYS | Richard Henderson | 2022-10-18 | 1 | -28/+95 |
| * | target/i386: Introduce structures for mmu_translate | Richard Henderson | 2022-10-18 | 1 | -154/+174 |
