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path: root/target/loongarch/translate.c
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* target/loongarch: Separate the hardware flags into MMU index and PLVRui Wang2022-11-071-2/+3
* target/loongarch: Adjust the layout of hardware flags bit fieldsRui Wang2022-11-041-1/+5
* target/loongarch: Convert to tcg_ops restore_state_to_opcRichard Henderson2022-10-261-6/+0Star
* accel/tcg: Add pc and host_pc params to gen_intermediate_codeRichard Henderson2022-09-061-2/+4
* target/loongarch: Remove cpu_fcsr0Richard Henderson2022-08-091-3/+0Star
* target/loongarch: Add timer related instructions support.Xiaojuan Yang2022-06-061-0/+2
* target/loongarch: Add LoongArch CSR instructionXiaojuan Yang2022-06-061-1/+10
* target/loongarch: Add branch instruction translationSong Gao2022-06-061-0/+1
* target/loongarch: Add floating point load/store instruction translationSong Gao2022-06-061-0/+1
* target/loongarch: Add floating point move instruction translationSong Gao2022-06-061-0/+1
* target/loongarch: Add floating point conversion instruction translationSong Gao2022-06-061-0/+1
* target/loongarch: Add floating point comparison instruction translationSong Gao2022-06-061-0/+1
* target/loongarch: Add floating point arithmetic instruction translationSong Gao2022-06-061-0/+11
* target/loongarch: Add fixed point extra instruction translationSong Gao2022-06-061-0/+1
* target/loongarch: Add fixed point atomic instruction translationSong Gao2022-06-061-0/+1
* target/loongarch: Add fixed point load/store instruction translationSong Gao2022-06-061-0/+6
* target/loongarch: Add fixed point bit instruction translationSong Gao2022-06-061-0/+1
* target/loongarch: Add fixed point shift instruction translationSong Gao2022-06-061-0/+1
* target/loongarch: Add fixed point arithmetic instruction translationSong Gao2022-06-061-0/+83
* target/loongarch: Add main translation routinesSong Gao2022-06-061-0/+161
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