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path: root/target/microblaze/op_helper.c
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* target/microblaze: Use cc->do_unaligned_accessRichard Henderson2020-09-011-21/+0Star
* target/microblaze: Fix no-op mb_cpu_transaction_failedRichard Henderson2020-09-011-12/+13
* target/microblaze: Fix cpu unwind for stackprotRichard Henderson2020-09-011-1/+5
* target/microblaze: Fix cpu unwind for fpu exceptionsRichard Henderson2020-09-011-17/+20
* target/microblaze: Unwind properly when raising divide-by-zeroRichard Henderson2020-09-011-11/+12
* target/microblaze: Implement cmp and cmpu inlineRichard Henderson2020-09-011-20/+0Star
* target/microblaze: Convert dec_sub to decodetreeRichard Henderson2020-09-011-16/+0Star
* target/microblaze: Remove empty D macrosRichard Henderson2020-09-011-2/+0Star
* target/microblaze: Remove helper_debug and env->debugRichard Henderson2020-09-011-23/+0Star
* target/microblaze: Fix width of ESRRichard Henderson2020-09-011-1/+1
* target/microblaze: Fix width of MSRRichard Henderson2020-09-011-1/+1
* target/microblaze: Fix width of PC and BTARGETRichard Henderson2020-09-011-2/+2
* target/microblaze: Split out FSR from env->sregsRichard Henderson2020-09-011-4/+4
* target/microblaze: Split out ESR from env->sregsRichard Henderson2020-09-011-9/+8Star
* target/microblaze: Split out EAR from env->sregsRichard Henderson2020-09-011-4/+4
* target/microblaze: Split out MSR from env->sregsRichard Henderson2020-09-011-11/+11
* target/microblaze: Split out PC from env->sregsRichard Henderson2020-09-011-1/+1
* target/microblaze: Add the div-zero-exception propertyEdgar E. Iglesias2020-04-301-2/+3
* target/microblaze: Use env_cpu, env_archcpuRichard Henderson2019-06-101-1/+1
* target/microblaze: Convert to CPUClass::tlb_fillRichard Henderson2019-05-101-19/+0Star
* target/microblaze: Switch to transaction_failed hookPeter Maydell2019-01-221-10/+12
* target-microblaze: Convert env_btarget to i64Edgar E. Iglesias2018-05-291-1/+1
* target-microblaze: Add support for extended access to TLBLOEdgar E. Iglesias2018-05-291-4/+4
* target-microblaze: Make special registers 64-bitEdgar E. Iglesias2018-05-291-4/+5
* target-microblaze: Use TCGv for load/store addressesEdgar E. Iglesias2018-05-291-4/+7
* target/*/cpu.h: remove softfloat.hAlex Bennée2018-02-211-0/+1
* accel/tcg: add size paremeter in tlb_fill()Laurent Vivier2018-01-251-3/+3
* target/*helper: don't check retaddr before calling cpu_restore_stateAlex Bennée2017-12-281-5/+2Star
* target-microblaze: Use clz opcodeRichard Henderson2017-01-101-5/+0Star
* Move target-* CPU file into a target/ folderThomas Huth2016-12-201-0/+523