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path: root/target/mips/op_helper.c
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* target/mips: Extract MSA helpers from op_helper.cPhilippe Mathieu-Daudé2021-01-141-394/+0Star
* target/mips: Extract FPU helpers to 'fpu_helper.h'Philippe Mathieu-Daudé2021-01-141-1/+1
* target/mips: Remove unused headers from op_helper.cPhilippe Mathieu-Daudé2020-12-131-4/+0Star
* target/mips: Fix Lesser GPL version numberChetan Pant2020-11-031-1/+1
* target/mips/op_helper: Log unimplemented cache opcodePhilippe Mathieu-Daudé2020-10-171-0/+9
* target/mips/op_helper: Document Invalidate/Writeback opcodes as no-opPhilippe Mathieu-Daudé2020-10-171-0/+5
* target/mips/op_helper: Convert multiple if() to switch casePhilippe Mathieu-Daudé2020-10-171-4/+9
* target/mips: Separate FPU-related helpers into their own fileAleksandar Markovic2020-02-041-1877/+0Star
* target/mips: Separate CP0-related helpers into their own fileAleksandar Markovic2020-02-041-1644/+3Star
* target/mips: Fix handling of LL/SC instructions after 7dd547e5abAlex Richardson2020-02-041-4/+4
* target/mips: Add implementation of GINVT instructionYongbok Kim2020-01-291-19/+110
* target/mips: Amend CP0 WatchHi register implementationYongbok Kim2020-01-291-2/+21
* target/mips: Use cpu_*_mmuidx_ra instead of MMU_MODE*_SUFFIXRichard Henderson2020-01-161-122/+60Star
* target/mips: Clean up op_helper.cAleksandar Markovic2019-10-251-347/+663
* target/mips: Switch to do_transaction_failed() hookPeter Maydell2019-09-121-16/+8Star
* Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20190903' into stagingPeter Maydell2019-09-041-7/+6Star
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| * mips/tcg: Call probe_write() for CONFIG_USER_ONLY as wellDavid Hildenbrand2019-09-031-5/+3Star
| * target/mips: Hard code size with MO_{8|16|32|64}Tony Nguyen2019-09-031-2/+2
| * target/mips: Access MemoryRegion with MemOpTony Nguyen2019-09-031-2/+3
* | target/mips: Fix emulation of ST.W in system modeAleksandar Markovic2019-08-291-8/+8
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* target/mips: rationalise softfloat includesAlex Bennée2019-08-191-0/+1
* target/mips: Use env_cpu, env_archcpuRichard Henderson2019-06-101-14/+11Star
* target/mips: Fix MSA instructions ST.<B|H|W|D> on big endian hostMateja Marjanovic2019-05-261-20/+180
* target/mips: Fix MSA instructions LD.<B|H|W|D> on big endian hostMateja Marjanovic2019-05-261-20/+168
* target/mips: Convert to CPUClass::tlb_fillRichard Henderson2019-05-101-15/+0Star
* target/mips: hold BQL in mips_vpe_wake()Goran Ferenc2019-02-141-0/+3
* hw/mips_int: hold BQL for all interrupt requestsAleksandar Markovic2019-02-141-18/+3Star
* target/mips: reimplement SC instruction emulation and use cmpxchgLeon Alrae2019-02-141-27/+0Star
* target/mips: compare virtual addresses in LL/SC sequenceLeon Alrae2019-02-141-12/+17
* target/mips: Update ITU to utilize SAARI and SAAR CP0 registersYongbok Kim2019-01-181-0/+14
* target/mips: Provide R/W access to SAARI and SAAR CP0 registersYongbok Kim2019-01-181-0/+50
* target/mips: Implement hardware page table walker for MIPS32Yongbok Kim2018-10-181-1/+6
* target/mips: Add CP0 PWCtl registerYongbok Kim2018-10-181-0/+10
* target/mips: Add CP0 PWSize registerYongbok Kim2018-10-181-0/+9
* target/mips: Add CP0 PWField registerYongbok Kim2018-10-181-0/+62
* target/mips: Fix ERET/ERETNC behavior related to ADEL exceptionYongbok Kim2018-08-241-1/+3
* target/mips: Implement emulation of nanoMIPS ROTX instructionMatthew Fortune2018-08-241-0/+94
* target/mips: Don't update BadVAddr register in Debug ModeYongbok Kim2018-08-161-3/+9
* target/mips: Raise a RI when given fs is n/a from CTC1Yongbok Kim2018-06-271-0/+3
* target/mips: Remove floatX_maybe_silence_nan from conversionsRichard Henderson2018-05-181-2/+0Star
* accel/tcg: add size paremeter in tlb_fill()Laurent Vivier2018-01-251-5/+5
* mips: introduce internal.h and cleanup cpu.hPhilippe Mathieu-Daudé2017-09-211-0/+1
* target-mips: apply CP0.PageMask before writing into TLB entryLeon Alrae2017-08-021-2/+3
* target/mips: Add segmentation control registersJames Hogan2017-07-201-0/+24
* target/mips: Add an MMU mode for ERLJames Hogan2017-07-201-0/+10
* target/mips: Abstract mmu_idx from hflagsJames Hogan2017-07-201-2/+2
* target/mips: Add CP0_Ebase.WG (write gate) supportJames Hogan2017-07-201-2/+10
* target/mips: Weaken TLB flush on UX,SX,KX,ASID changesJames Hogan2017-07-201-1/+1
* target/mips: Fix TLBWI shadow flush for EHINV,XI,RIJames Hogan2017-07-201-2/+10
* target/mips: hold BQL for timer interruptsYongbok Kim2017-03-091-3/+18
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