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path: root/target/mips/op_helper.c
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* target/mips: Update ITU to utilize SAARI and SAAR CP0 registersYongbok Kim2019-01-181-0/+14
* target/mips: Provide R/W access to SAARI and SAAR CP0 registersYongbok Kim2019-01-181-0/+50
* target/mips: Implement hardware page table walker for MIPS32Yongbok Kim2018-10-181-1/+6
* target/mips: Add CP0 PWCtl registerYongbok Kim2018-10-181-0/+10
* target/mips: Add CP0 PWSize registerYongbok Kim2018-10-181-0/+9
* target/mips: Add CP0 PWField registerYongbok Kim2018-10-181-0/+62
* target/mips: Fix ERET/ERETNC behavior related to ADEL exceptionYongbok Kim2018-08-241-1/+3
* target/mips: Implement emulation of nanoMIPS ROTX instructionMatthew Fortune2018-08-241-0/+94
* target/mips: Don't update BadVAddr register in Debug ModeYongbok Kim2018-08-161-3/+9
* target/mips: Raise a RI when given fs is n/a from CTC1Yongbok Kim2018-06-271-0/+3
* target/mips: Remove floatX_maybe_silence_nan from conversionsRichard Henderson2018-05-181-2/+0Star
* accel/tcg: add size paremeter in tlb_fill()Laurent Vivier2018-01-251-5/+5
* mips: introduce internal.h and cleanup cpu.hPhilippe Mathieu-Daudé2017-09-211-0/+1
* target-mips: apply CP0.PageMask before writing into TLB entryLeon Alrae2017-08-021-2/+3
* target/mips: Add segmentation control registersJames Hogan2017-07-201-0/+24
* target/mips: Add an MMU mode for ERLJames Hogan2017-07-201-0/+10
* target/mips: Abstract mmu_idx from hflagsJames Hogan2017-07-201-2/+2
* target/mips: Add CP0_Ebase.WG (write gate) supportJames Hogan2017-07-201-2/+10
* target/mips: Weaken TLB flush on UX,SX,KX,ASID changesJames Hogan2017-07-201-1/+1
* target/mips: Fix TLBWI shadow flush for EHINV,XI,RIJames Hogan2017-07-201-2/+10
* target/mips: hold BQL for timer interruptsYongbok Kim2017-03-091-3/+18
* cputlb: drop flush_global flag from tlb_flushAlex Bennée2017-01-131-4/+4
* target-mips: Use clz opcodeRichard Henderson2017-01-101-22/+0Star
* Move target-* CPU file into a target/ folderThomas Huth2016-12-201-0/+4196
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