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Experimental fork of QEMU with video encoding patches
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mips
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tcg
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msa_translate.c
Commit message (
Expand
)
Author
Age
Files
Lines
*
target/mips: Fix FTRUNC_S and FTRUNC_U trans helper
Ni Hui
2022-06-11
1
-2
/
+2
*
target/mips: Do not treat msa INSERT as NOP when wd is zero
Ni Hui
2022-06-11
1
-5
/
+10
*
target/mips: Fix msa checking condition in trans_msa_elm_fn()
Ni Hui
2022-06-11
1
-1
/
+1
*
target/mips: Fix df_extract_val() and df_extract_df() dfe lookup
Ni Hui
2022-06-11
1
-3
/
+3
*
target/mips: Fix SAT_S trans helper
Ni Hui
2022-06-11
1
-1
/
+1
*
target/mips: Remove generic MSA opcode
Philippe Mathieu-Daudé
2021-11-02
1
-7
/
+0
*
target/mips: Convert CTCMSA opcode to decodetree
Philippe Mathieu-Daudé
2021-11-02
1
-57
/
+12
*
target/mips: Convert CFCMSA opcode to decodetree
Philippe Mathieu-Daudé
2021-11-02
1
-8
/
+19
*
target/mips: Convert MSA MOVE.V opcode to decodetree
Philippe Mathieu-Daudé
2021-11-02
1
-5
/
+14
*
target/mips: Convert MSA COPY_S and INSERT opcodes to decodetree
Philippe Mathieu-Daudé
2021-11-02
1
-88
/
+17
*
target/mips: Convert MSA COPY_U opcode to decodetree
Philippe Mathieu-Daudé
2021-11-02
1
-26
/
+40
*
target/mips: Convert MSA ELM instruction format to decodetree
Philippe Mathieu-Daudé
2021-11-02
1
-13
/
+44
*
target/mips: Convert MSA 3R instruction format to decodetree (part 4/4)
Philippe Mathieu-Daudé
2021-11-02
1
-863
/
+53
*
target/mips: Convert MSA 3R instruction format to decodetree (part 3/4)
Philippe Mathieu-Daudé
2021-11-02
1
-34
/
+6
*
target/mips: Convert MSA 3R instruction format to decodetree (part 2/4)
Philippe Mathieu-Daudé
2021-11-02
1
-158
/
+24
*
target/mips: Convert MSA 3R instruction format to decodetree (part 1/4)
Philippe Mathieu-Daudé
2021-11-02
1
-12
/
+5
*
target/mips: Convert MSA 3RF instruction format to decodetree (DF_WORD)
Philippe Mathieu-Daudé
2021-11-02
1
-176
/
+37
*
target/mips: Convert MSA 3RF instruction format to decodetree (DF_HALF)
Philippe Mathieu-Daudé
2021-11-02
1
-39
/
+29
*
target/mips: Convert MSA VEC instruction format to decodetree
Philippe Mathieu-Daudé
2021-11-02
1
-75
/
+23
*
target/mips: Convert MSA 2R instruction format to decodetree
Philippe Mathieu-Daudé
2021-11-02
1
-75
/
+16
*
target/mips: Convert MSA FILL opcode to decodetree
Philippe Mathieu-Daudé
2021-11-02
1
-12
/
+19
*
target/mips: Convert MSA 2RF instruction format to decodetree
Philippe Mathieu-Daudé
2021-11-02
1
-85
/
+33
*
target/mips: Convert MSA load/store instruction format to decodetree
Philippe Mathieu-Daudé
2021-11-02
1
-59
/
+32
*
target/mips: Convert MSA I8 instruction format to decodetree
Philippe Mathieu-Daudé
2021-11-02
1
-56
/
+19
*
target/mips: Convert MSA SHF opcode to decodetree
Philippe Mathieu-Daudé
2021-11-02
1
-17
/
+19
*
target/mips: Convert MSA BIT instruction format to decodetree
Philippe Mathieu-Daudé
2021-11-02
1
-97
/
+82
*
target/mips: Convert MSA I5 instruction format to decodetree
Philippe Mathieu-Daudé
2021-11-02
1
-77
/
+25
*
target/mips: Convert MSA LDI opcode to decodetree
Philippe Mathieu-Daudé
2021-11-02
1
-8
/
+14
*
target/mips: Rename sa16 -> sa, bz_df -> bz -> bz_v
Philippe Mathieu-Daudé
2021-11-02
1
-10
/
+10
*
target/mips: Use enum definitions from CPUMIPSMSADataFormat enum
Philippe Mathieu-Daudé
2021-11-02
1
-3
/
+3
*
target/mips: Have check_msa_access() return a boolean
Philippe Mathieu-Daudé
2021-11-02
1
-7
/
+18
*
target/mips: Use dup_const() to simplify
Philippe Mathieu-Daudé
2021-11-02
1
-20
/
+3
*
target/mips: Adjust style in msa_translate_init()
Philippe Mathieu-Daudé
2021-11-02
1
-1
/
+3
*
target/mips: Use explicit extract32() calls in gen_msa_i5()
Philippe Mathieu-Daudé
2021-10-18
1
-7
/
+4
*
target/mips: Use tcg_constant_i32() in gen_msa_3rf()
Philippe Mathieu-Daudé
2021-10-18
1
-9
/
+14
*
target/mips: Use tcg_constant_i32() in gen_msa_2r()
Philippe Mathieu-Daudé
2021-10-18
1
-3
/
+2
*
target/mips: Use tcg_constant_i32() in gen_msa_2rf()
Philippe Mathieu-Daudé
2021-10-18
1
-2
/
+1
*
target/mips: Use tcg_constant_i32() in gen_msa_elm_df()
Philippe Mathieu-Daudé
2021-10-18
1
-2
/
+1
*
target/mips: Remove unused register from MSA 2R/2RF instruction format
Philippe Mathieu-Daudé
2021-10-18
1
-6
/
+0
*
target/mips: Rename 'rtype' as 'r'
Philippe Mathieu-Daudé
2021-08-25
1
-2
/
+2
*
target/mips: Merge msa32/msa64 decodetree definitions
Philippe Mathieu-Daudé
2021-06-24
1
-10
/
+4
*
target/mips: Remove pointless gen_msa()
Philippe Mathieu-Daudé
2021-06-24
1
-6
/
+1
*
target/mips: Optimize regnames[] arrays
Philippe Mathieu-Daudé
2021-06-24
1
-1
/
+1
*
target/mips: Move TCG source files under tcg/ sub directory
Philippe Mathieu-Daudé
2021-05-02
1
-0
/
+2286