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* Remove qemu-common.h include from most unitsMarc-André Lureau2022-04-061-1/+0Star
* Replace TARGET_WORDS_BIGENDIANMarc-André Lureau2022-04-062-7/+7
* Replace config-time define HOST_WORDS_BIGENDIANMarc-André Lureau2022-04-063-29/+29
* target/mips: Fix address space range declaration on n32WANG Xuerui2022-03-291-1/+1
* Merge remote-tracking branch 'remotes/philmd/tags/mips-20220308' into stagingPeter Maydell2022-03-093-19/+10Star
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| * target/mips: Remove duplicated MIPSCPU::cp0_count_ratePhilippe Mathieu-Daudé2022-03-073-19/+9Star
| * target/mips: Fix cycle counter timing calculationsSimon Burge2022-03-071-1/+2
* | target: Use ArchCPU as interface to target CPUPhilippe Mathieu-Daudé2022-03-061-1/+1
* | target: Introduce and use OBJECT_DECLARE_CPU_TYPE() macroPhilippe Mathieu-Daudé2022-03-062-4/+1Star
* | target: Use CPUArchState as interface to target-specific CPU statePhilippe Mathieu-Daudé2022-03-061-4/+2Star
* | target: Use forward declared type instead of structure typePhilippe Mathieu-Daudé2022-03-061-7/+7
* | target: Include missing 'cpu.h'Philippe Mathieu-Daudé2022-03-061-0/+1
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* exec/exec-all: Move 'qemu/log.h' include in units requiring itPhilippe Mathieu-Daudé2022-02-213-0/+3
* target/mips: Extract trap code into env->error_codeRichard Henderson2022-01-113-8/+24
* target/mips: Extract break code into env->error_codeRichard Henderson2022-01-114-5/+16
* exec/memop: Adding signedness to quad definitionsFrédéric Pétrot2022-01-083-38/+38
* Merge remote-tracking branch 'remotes/philmd/tags/mips-20211102' into stagingRichard Henderson2021-11-024-2087/+845Star
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| * target/mips: Remove obsolete FCR0_HAS2008 comment on P5600 CPUPhilippe Mathieu-Daudé2021-11-021-1/+0Star
| * target/mips: Fix Loongson-3A4000 MSAIR config registerPhilippe Mathieu-Daudé2021-11-021-0/+1
| * target/mips: Remove one MSA unnecessary decodetree overlap groupPhilippe Mathieu-Daudé2021-11-021-182/+180Star
| * target/mips: Remove generic MSA opcodePhilippe Mathieu-Daudé2021-11-022-9/+0Star
| * target/mips: Convert CTCMSA opcode to decodetreePhilippe Mathieu-Daudé2021-11-022-58/+16Star
| * target/mips: Convert CFCMSA opcode to decodetreePhilippe Mathieu-Daudé2021-11-022-9/+23
| * target/mips: Convert MSA MOVE.V opcode to decodetreePhilippe Mathieu-Daudé2021-11-022-6/+20
| * target/mips: Convert MSA COPY_S and INSERT opcodes to decodetreePhilippe Mathieu-Daudé2021-11-022-88/+19Star
| * target/mips: Convert MSA COPY_U opcode to decodetreePhilippe Mathieu-Daudé2021-11-022-26/+41
| * target/mips: Convert MSA ELM instruction format to decodetreePhilippe Mathieu-Daudé2021-11-022-13/+52
| * target/mips: Convert MSA 3R instruction format to decodetree (part 4/4)Philippe Mathieu-Daudé2021-11-022-863/+106Star
| * target/mips: Convert MSA 3R instruction format to decodetree (part 3/4)Philippe Mathieu-Daudé2021-11-022-34/+9Star
| * target/mips: Convert MSA 3R instruction format to decodetree (part 2/4)Philippe Mathieu-Daudé2021-11-022-158/+35Star
| * target/mips: Convert MSA 3R instruction format to decodetree (part 1/4)Philippe Mathieu-Daudé2021-11-022-12/+11Star
| * target/mips: Convert MSA 3RF instruction format to decodetree (DF_WORD)Philippe Mathieu-Daudé2021-11-022-176/+76Star
| * target/mips: Convert MSA 3RF instruction format to decodetree (DF_HALF)Philippe Mathieu-Daudé2021-11-022-39/+38Star
| * target/mips: Convert MSA VEC instruction format to decodetreePhilippe Mathieu-Daudé2021-11-022-75/+31Star
| * target/mips: Convert MSA 2R instruction format to decodetreePhilippe Mathieu-Daudé2021-11-022-75/+19Star
| * target/mips: Convert MSA FILL opcode to decodetreePhilippe Mathieu-Daudé2021-11-022-12/+21
| * target/mips: Convert MSA 2RF instruction format to decodetreePhilippe Mathieu-Daudé2021-11-022-85/+53Star
| * target/mips: Convert MSA load/store instruction format to decodetreePhilippe Mathieu-Daudé2021-11-022-59/+36Star
| * target/mips: Convert MSA I8 instruction format to decodetreePhilippe Mathieu-Daudé2021-11-022-56/+27Star
| * target/mips: Convert MSA SHF opcode to decodetreePhilippe Mathieu-Daudé2021-11-022-17/+22
| * target/mips: Convert MSA BIT instruction format to decodetreePhilippe Mathieu-Daudé2021-11-022-97/+101
| * target/mips: Convert MSA I5 instruction format to decodetreePhilippe Mathieu-Daudé2021-11-022-77/+41Star
| * target/mips: Convert MSA LDI opcode to decodetreePhilippe Mathieu-Daudé2021-11-022-9/+21
| * target/mips: Rename sa16 -> sa, bz_df -> bz -> bz_vPhilippe Mathieu-Daudé2021-11-022-18/+17Star
| * target/mips: Use enum definitions from CPUMIPSMSADataFormat enumPhilippe Mathieu-Daudé2021-11-021-3/+3
| * target/mips: Have check_msa_access() return a booleanPhilippe Mathieu-Daudé2021-11-021-7/+18
| * target/mips: Use dup_const() to simplifyPhilippe Mathieu-Daudé2021-11-021-20/+3Star
| * target/mips: Adjust style in msa_translate_init()Philippe Mathieu-Daudé2021-11-021-1/+3
| * target/mips: Fix MSA MSUBV.B opcodePhilippe Mathieu-Daudé2021-11-021-16/+16
| * target/mips: Fix MSA MADDV.B opcodePhilippe Mathieu-Daudé2021-11-021-16/+16
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