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* tcg: Make tb arg to synchronize_from_tb constRichard Henderson2021-01-071-1/+2
* target/mips: Don't use clock_get_ns() in clock period calculationPeter Maydell2021-01-041-2/+2
* Merge remote-tracking branch 'remotes/armbru/tags/pull-qapi-2020-12-19' into ...Peter Maydell2021-01-012-7/+3Star
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| * migration: Replace migration's JSON writer by the general oneMarkus Armbruster2020-12-191-2/+2
| * qapi: Use QAPI_LIST_PREPEND() where possibleEric Blake2020-12-191-5/+1Star
* | linux-user/elfload: Introduce MIPS GET_FEATURE_REG_EQU() macroPhilippe Mathieu-Daudé2020-12-171-0/+1
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* target/mips: Use FloatRoundMode enum for FCR31 modes conversionPhilippe Mathieu-Daudé2020-12-132-2/+3
* target/mips: Remove unused headers from fpu_helper.cPhilippe Mathieu-Daudé2020-12-131-4/+0Star
* target/mips: Inline cpu_mips_realize_env() in mips_cpu_realizefn()Philippe Mathieu-Daudé2020-12-131-12/+8Star
* target/mips: Move cpu definitions, reset() and realize() to cpu.cPhilippe Mathieu-Daudé2020-12-133-244/+243Star
* target/mips: Move mips_cpu_add_definition() from helper.c to cpu.cPhilippe Mathieu-Daudé2020-12-132-33/+33
* target/mips: Extract cpu_supports*/cpu_set* translate.cPhilippe Mathieu-Daudé2020-12-132-18/+18
* target/mips: Do not initialize MT registers if MT ASE absentPhilippe Mathieu-Daudé2020-12-131-0/+4
* target/mips: Introduce ase_mt_available() helperPhilippe Mathieu-Daudé2020-12-135-4/+11
* target/mips: Remove mips_def_t unused argument from mvp_init()Philippe Mathieu-Daudé2020-12-132-2/+2
* target/mips: Remove unused headers from op_helper.cPhilippe Mathieu-Daudé2020-12-131-4/+0Star
* target/mips: Remove unused headers from translate.cPhilippe Mathieu-Daudé2020-12-131-2/+0Star
* hw/mips: Move address translation helpers to target/mips/Philippe Mathieu-Daudé2020-12-134-2/+60
* target/mips: Introduce cpu_supports_isa() taking CPUMIPSState argumentPhilippe Mathieu-Daudé2020-12-132-0/+6
* target/mips: Rename cpu_supports_FEAT() as cpu_type_supports_FEAT()Philippe Mathieu-Daudé2020-12-132-4/+4
* target/mips: Explicit Release 6 MMU typesPhilippe Mathieu-Daudé2020-12-131-4/+5
* target/mips: Allow executing MSA instructions on Loongson-3A4000Philippe Mathieu-Daudé2020-12-131-2/+2
* target/mips: Also display exception names in user-modePhilippe Mathieu-Daudé2020-12-131-11/+14
* target/mips: Remove unused headers from cp0_helper.cPhilippe Mathieu-Daudé2020-12-131-3/+1Star
* target/mips: Do not include CP0 helpers in user-mode emulationPhilippe Mathieu-Daudé2020-12-132-5/+1Star
* target/mips: Replace magic values by CP0PM_MASK or TARGET_PAGE_BITS_MINPhilippe Mathieu-Daudé2020-12-132-4/+5
* target/mips: Include "exec/memattrs.h" in 'internal.h'Philippe Mathieu-Daudé2020-12-132-1/+1
* target/mips/kvm: Remove unused headersPhilippe Mathieu-Daudé2020-12-131-2/+0Star
* target/mips/kvm: Assert unreachable code is not usedPhilippe Mathieu-Daudé2020-12-131-6/+2Star
* target/mips: Fix PageMask with variable page sizeJiaxun Yang2020-11-092-6/+22
* target/mips: Add unaligned access support for MIPS64R6 and Loongson-3Huacai Chen2020-11-031-2/+2
* target/mips: Fix Lesser GPL version numberChetan Pant2020-11-0311-11/+11
* target/mips: Increase number of TLB entries on the 34Kf core (16 -> 64)Philippe Mathieu-Daudé2020-10-171-1/+1
* target/mips/cpu: Display warning when CPU is used without input clockPhilippe Mathieu-Daudé2020-10-171-0/+10
* target/mips/cpu: Introduce mips_cpu_create_with_clock() helperPhilippe Mathieu-Daudé2020-10-172-0/+24
* target/mips/cpu: Allow the CPU to use dynamic frequenciesPhilippe Mathieu-Daudé2020-10-172-2/+13
* target/mips/cpu: Make cp0_count_rate a propertyPhilippe Mathieu-Daudé2020-10-172-8/+20
* target/mips/cpu: Calculate the CP0 timer period using the CPU frequencyPhilippe Mathieu-Daudé2020-10-171-2/+2
* target/mips: Move cp0_count_ns to CPUMIPSStatePhilippe Mathieu-Daudé2020-10-173-17/+28
* target/mips/cp0_timer: Document TIMER_PERIOD originPhilippe Mathieu-Daudé2020-10-171-1/+11
* target/mips/cp0_timer: Explicit unit in variable namePhilippe Mathieu-Daudé2020-10-171-9/+10
* target/mips: Move cpu_mips_get_random() with CP0 helpersPhilippe Mathieu-Daudé2020-10-173-26/+26
* target/mips/op_helper: Log unimplemented cache opcodePhilippe Mathieu-Daudé2020-10-171-0/+9
* target/mips/op_helper: Document Invalidate/Writeback opcodes as no-opPhilippe Mathieu-Daudé2020-10-171-0/+5
* target/mips/op_helper: Convert multiple if() to switch casePhilippe Mathieu-Daudé2020-10-171-4/+9
* target/mips: Add loongson-ext lsdc2 group of instructionsJiaxun Yang2020-10-171-0/+179
* target/mips: Add loongson-ext lswc2 group of instructions (Part 2)Jiaxun Yang2020-10-171-2/+180
* target/mips: Add loongson-ext lswc2 group of instructions (Part 1)Jiaxun Yang2020-10-171-0/+86
* target/mips: Demacro helpers for <MAX|MAXA|MIN|MINA>.<D|S>Aleksandar Markovic2020-10-171-23/+81
* target/mips: Demacro helpers for M<ADD|SUB>F.<D|S>Aleksandar Markovic2020-10-171-17/+46
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