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* target/nios2: Prevent writes to read-only or reserved control fieldsRichard Henderson2022-04-261-0/+13
| | | | | | | | | | Create an array of masks which detail the writable and readonly bits for each control register. Apply them when writing to control registers, including the write to status during eret. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20220421151735.31996-38-richard.henderson@linaro.org>
* target/nios2: Clean up handling of tlbmisc in do_exceptionRichard Henderson2022-04-261-6/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The 4 lower bits, D, PERM, BAD, DBL, are unconditionally set on any exception with EH=0, or so says Table 42 (Processor Status After Taking Exception). We currently do not set PERM or BAD at all, and only set/clear DBL for tlb miss, and do not clear DBL for any other exception. It is a bit confusing to set D in tlb_fill and the rest during do_interrupt, so move the setting of D to do_interrupt as well. To do this, split EXP_TLBD into two cases, EXCP_TLB_X and EXCP_TLB_D, which allows us to distinguish them during do_interrupt. Choose a value for EXCP_TLB_D such that when truncated it produces the correct value for exception.CAUSE. Rename EXCP_TLB[RWX] to EXCP_PERM_[RWX], to emphasize that the exception is permissions related. Rename EXCP_SUPER[AD] to EXCP_SUPERA_[DX] to emphasize that they are both "supervisor address" exceptions, data and execute. Retain the setting of tlbmisc.WE for the fast-tlb-miss path, as it is being relied upon, but remove it from the permission path. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220421151735.31996-37-richard.henderson@linaro.org>
* target/nios2: Create EXCP_SEMIHOST for semi-hostingRichard Henderson2022-04-261-0/+1
| | | | | | | | | Decode 'break 1' during translation, rather than doing it again during exception processing. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220421151735.31996-32-richard.henderson@linaro.org>
* target/nios2: Move R_FOO and CR_BAR into enumerationsRichard Henderson2022-04-261-37/+35Star
| | | | | | | | These symbols become available to the debugger. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220421151735.31996-31-richard.henderson@linaro.org>
* target/nios2: Use hw/registerfields.h for CR_TLBMISC fieldsRichard Henderson2022-04-261-10/+19
| | | | | | | | | Use FIELD_EX32 and FIELD_DP32 instead of managing the masking by hand. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220421151735.31996-30-richard.henderson@linaro.org>
* target/nios2: Rename CR_TLBMISC_WR to CR_TLBMISC_WERichard Henderson2022-04-261-1/+1
| | | | | | | | WE is the architectural name of the field, not WR. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220421151735.31996-29-richard.henderson@linaro.org>
* target/nios2: Use hw/registerfields.h for CR_TLBACC fieldsRichard Henderson2022-04-261-8/+15
| | | | | | | | | | | | | | Retain the helper macros for single bit fields as aliases to the longer R_*_MASK names. Use FIELD_EX32 and FIELD_DP32 instead of manually manipulating the fields. Since we're rewriting the references to CR_TLBACC_IGN_* anyway, we correct the name of this field to IG, which is its name in the official CPU documentation. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220421151735.31996-28-richard.henderson@linaro.org>
* target/nios2: Use hw/registerfields.h for CR_TLBADDR fieldsRichard Henderson2022-04-261-4/+4
| | | | | | | | | Use FIELD_EX32 and FIELD_DP32 instead of manual manipulation of the fields. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220421151735.31996-27-richard.henderson@linaro.org>
* target/nios2: Use hw/registerfields.h for CR_EXCEPTION fieldsRichard Henderson2022-04-261-0/+4
| | | | | | | | Use FIELD_DP32 instead of manual shifting and masking. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220421151735.31996-26-richard.henderson@linaro.org>
* target/nios2: Use hw/registerfields.h for CR_STATUS fieldsRichard Henderson2022-04-261-9/+19
| | | | | | | | | Add all fields; retain the helper macros for single bit fields. So far there are no uses of the multi-bit status fields. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220421151735.31996-25-richard.henderson@linaro.org>
* target/nios2: Split control registers away from general registersRichard Henderson2022-04-261-23/+20Star
| | | | | | | | Place the control registers into their own array, env->ctrl[]. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220421151735.31996-23-richard.henderson@linaro.org>
* target/nios2: Remove cpu_interrupts_enabledRichard Henderson2022-04-261-5/+0Star
| | | | | | | | | This function is unused. The real computation of this value is located in nios2_cpu_exec_interrupt. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220421151735.31996-22-richard.henderson@linaro.org>
* target/nios2: Split PC out of env->regs[]Richard Henderson2022-04-261-6/+4Star
| | | | | | | | It is cleaner to have a separate name for this variable. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220421151735.31996-17-richard.henderson@linaro.org>
* target/nios2: Add NUM_GP_REGS and NUM_CP_REGSAmir Gonnen2022-04-261-2/+4
| | | | | | | | | | | Split NUM_CORE_REGS into components that can be used elsewhere. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Amir Gonnen <amir.gonnen@neuroblade.ai> Message-Id: <20220303153906.2024748-3-amir.gonnen@neuroblade.ai> [rth: Split out of a larger patch for shadow register sets.] Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220421151735.31996-16-richard.henderson@linaro.org>
* target/nios2: Remove nios2_cpu_record_sigsegvRichard Henderson2022-04-261-5/+1Star
| | | | | | | | | Since f5ef0e518d0, we have a real page mapped for kuser, which means the special casing for SIGSEGV can go away. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20220421151735.31996-11-richard.henderson@linaro.org>
* compiler.h: replace QEMU_NORETURN with G_NORETURNMarc-André Lureau2022-04-211-3/+3
| | | | | | | | | | | | | G_NORETURN was introduced in glib 2.68, fallback to G_GNUC_NORETURN in glib-compat. Note that this attribute must be placed before the function declaration (bringing a bit of consistency in qemu codebase usage). Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Reviewed-by: Warner Losh <imp@bsdimp.com> Message-Id: <20220420132624.2439741-20-marcandre.lureau@redhat.com>
* target: Use ArchCPU as interface to target CPUPhilippe Mathieu-Daudé2022-03-061-1/+1
| | | | | | | | | | ArchCPU is our interface with target-specific code. Use it as a forward-declared opaque pointer (abstract type), having its structure defined by each target. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20220214183144.27402-15-f4bug@amsat.org>
* target: Introduce and use OBJECT_DECLARE_CPU_TYPE() macroPhilippe Mathieu-Daudé2022-03-061-2/+1Star
| | | | | | | | | Replace the boilerplate code to declare CPU QOM types and macros, and forward-declare the CPU instance type. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20220214183144.27402-14-f4bug@amsat.org>
* target: Use CPUArchState as interface to target-specific CPU statePhilippe Mathieu-Daudé2022-03-061-2/+2
| | | | | | | | | | While CPUState is our interface with generic code, CPUArchState is our interface with target-specific code. Use CPUArchState as an abstract type, defined by each target. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20220214183144.27402-13-f4bug@amsat.org>
* target/nios2: Rewrite interrupt handlingRichard Henderson2022-03-031-1/+0Star
| | | | | | | | | | | | | Previously, we would avoid setting CPU_INTERRUPT_HARD when interrupts are disabled at a particular point in time, instead queuing the value into cpu->irq_pending. This is more complicated than required. Instead, set CPU_INTERRUPT_HARD any time there is a pending interrupt, and exclusively check for interrupts disabled in nios2_cpu_exec_interrupt. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* linux-user/nios2: Properly emulate EXCP_TRAPRichard Henderson2022-01-061-1/+1
| | | | | | | | | | | | | | The real kernel has to load the instruction and extract the imm5 field; for qemu, modify the translator to do this. The use of R_AT for this in cpu_loop was a bug. Handle the other trap numbers as per the kernel's trap_table. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20211221025012.1057923-2-richard.henderson@linaro.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
* target/nios2: Implement nios2_cpu_record_sigsegvRichard Henderson2021-11-021-0/+6
| | | | | | | | | Because the linux-user kuser page handling is currently implemented by detecting magic addresses in the unnamed 0xaa trap, we cannot simply remove nios2_cpu_tlb_fill and rely on the fallback code. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* hw/core: Make do_unaligned_access noreturnRichard Henderson2021-09-221-2/+2
| | | | | | | | | | While we may have had some thought of allowing system-mode to return from this hook, we have no guests that require this. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* include/exec: Move cpu_signal_handler declarationRichard Henderson2021-09-221-2/+0Star
| | | | | | | | | | There is nothing target specific about this. The implementation is host specific, but the declaration is 100% common. Reviewed-By: Warner Losh <imp@bsdimp.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/nios2: Move nios2_check_interrupts() into target/nios2Peter Maydell2020-12-151-2/+0Star
| | | | | | | | | | | | | | | The function nios2_check_interrupts)() looks only at CPU-internal state; it belongs in target/nios2, not hw/nios2. Move it into the same file as its only caller, so it can just be local to that file. This removes the only remaining code from cpu_pic.c, so we can delete that file entirely. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20201129174022.26530-3-peter.maydell@linaro.org Reviewed-by: Wentong Wu <wentong.wu@intel.com> Tested-by: Wentong Wu <wentong.wu@intel.com>
* target/nios2: Move IIC code into CPU object properPeter Maydell2020-12-151-1/+0Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Nios2 architecture supports two different interrupt controller options: * The IIC (Internal Interrupt Controller) is part of the CPU itself; it has 32 IRQ input lines and no NMI support. Interrupt status is queried and controlled via the CPU's ipending and istatus registers. * The EIC (External Interrupt Controller) interface allows the CPU to connect to an external interrupt controller. The interface allows the interrupt controller to present a packet of information containing: - handler address - interrupt level - register set - NMI mode QEMU does not model an EIC currently. We do model the IIC, but its implementation is split across code in hw/nios2/cpu_pic.c and hw/intc/nios2_iic.c. The code in those two files has no state of its own -- the IIC state is in the Nios2CPU state struct. Because CPU objects now inherit (indirectly) from TYPE_DEVICE, they can have GPIO input lines themselves, so we can implement the IIC directly in the CPU object the same way that real hardware does. Create named "IRQ" GPIO inputs to the Nios2 CPU object, and make the only user of the IIC wire up directly to those instead. Note that the old code had an "NMI" concept which was entirely unused and also as far as I can see not architecturally correct, since only the EIC has a concept of an NMI. This fixes a Coverity-reported trivial memory leak of the IRQ array allocated in nios2_cpu_pic_init(). Fixes: Coverity CID 1421916 Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20201129174022.26530-2-peter.maydell@linaro.org Reviewed-by: Wentong Wu <wentong.wu@intel.com> Tested-by: Wentong Wu <wentong.wu@intel.com>
* qom: Remove module_obj_name parameter from OBJECT_DECLARE* macrosEduardo Habkost2020-09-181-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | One of the goals of having less boilerplate on QOM declarations is to avoid human error. Requiring an extra argument that is never used is an opportunity for mistakes. Remove the unused argument from OBJECT_DECLARE_TYPE and OBJECT_DECLARE_SIMPLE_TYPE. Coccinelle patch used to convert all users of the macros: @@ declarer name OBJECT_DECLARE_TYPE; identifier InstanceType, ClassType, lowercase, UPPERCASE; @@ OBJECT_DECLARE_TYPE(InstanceType, ClassType, - lowercase, UPPERCASE); @@ declarer name OBJECT_DECLARE_SIMPLE_TYPE; identifier InstanceType, lowercase, UPPERCASE; @@ OBJECT_DECLARE_SIMPLE_TYPE(InstanceType, - lowercase, UPPERCASE); Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Acked-by: Cornelia Huck <cohuck@redhat.com> Acked-by: Igor Mammedov <imammedo@redhat.com> Acked-by: Paul Durrant <paul@xen.org> Acked-by: Thomas Huth <thuth@redhat.com> Message-Id: <20200916182519.415636-4-ehabkost@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
* Use OBJECT_DECLARE_TYPE where possibleEduardo Habkost2020-09-091-4/+2Star
| | | | | | | | | | | | | | | | Replace DECLARE_OBJ_CHECKERS with OBJECT_DECLARE_TYPE where the typedefs can be safely removed. Generated running: $ ./scripts/codeconverter/converter.py -i \ --pattern=DeclareObjCheckers $(git grep -l '' -- '*.[ch]') Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Message-Id: <20200831210740.126168-16-ehabkost@redhat.com> Message-Id: <20200831210740.126168-17-ehabkost@redhat.com> Message-Id: <20200831210740.126168-18-ehabkost@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
* Use DECLARE_*CHECKER* macrosEduardo Habkost2020-09-091-6/+2Star
| | | | | | | | | | | | | | | Generated using: $ ./scripts/codeconverter/converter.py -i \ --pattern=TypeCheckMacro $(git grep -l '' -- '*.[ch]') Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Reviewed-by: Juan Quintela <quintela@redhat.com> Message-Id: <20200831210740.126168-12-ehabkost@redhat.com> Reviewed-by: Juan Quintela <quintela@redhat.com> Message-Id: <20200831210740.126168-13-ehabkost@redhat.com> Message-Id: <20200831210740.126168-14-ehabkost@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
* Move QOM typedefs and add missing includesEduardo Habkost2020-09-091-4/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some typedefs and macros are defined after the type check macros. This makes it difficult to automatically replace their definitions with OBJECT_DECLARE_TYPE. Patch generated using: $ ./scripts/codeconverter/converter.py -i \ --pattern=QOMStructTypedefSplit $(git grep -l '' -- '*.[ch]') which will split "typdef struct { ... } TypedefName" declarations. Followed by: $ ./scripts/codeconverter/converter.py -i --pattern=MoveSymbols \ $(git grep -l '' -- '*.[ch]') which will: - move the typedefs and #defines above the type check macros - add missing #include "qom/object.h" lines if necessary Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Reviewed-by: Juan Quintela <quintela@redhat.com> Message-Id: <20200831210740.126168-9-ehabkost@redhat.com> Reviewed-by: Juan Quintela <quintela@redhat.com> Message-Id: <20200831210740.126168-10-ehabkost@redhat.com> Message-Id: <20200831210740.126168-11-ehabkost@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
* cpu: Use DeviceClass reset instead of a special CPUClass resetPeter Maydell2020-03-181-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The CPUClass has a 'reset' method. This is a legacy from when TYPE_CPU used not to inherit from TYPE_DEVICE. We don't need it any more, as we can simply use the TYPE_DEVICE reset. The 'cpu_reset()' function is kept as the API which most places use to reset a CPU; it is now a wrapper which calls device_cold_reset() and then the tracepoint function. This change should not cause CPU objects to be reset more often than they are at the moment, because: * nobody is directly calling device_cold_reset() or qdev_reset_all() on CPU objects * no CPU object is on a qbus, so they will not be reset either by somebody calling qbus_reset_all()/bus_cold_reset(), or by the main "reset sysbus and everything in the qbus tree" reset that most devices are reset by Note that this does not change the need for each machine or whatever to use qemu_register_reset() to arrange to call cpu_reset() -- that is necessary because CPU objects are not on any qbus, so they don't get reset when the qbus tree rooted at the sysbus bus is reset, and this isn't being changed here. All the changes to the files under target/ were made using the included Coccinelle script, except: (1) the deletion of the now-inaccurate and not terribly useful "CPUClass::reset" comments was done with a perl one-liner afterwards: perl -n -i -e '/ CPUClass::reset/ or print' target/*/*.c (2) this bit of the s390 change was done by hand, because the Coccinelle script is not sophisticated enough to handle the parent_reset call being inside another function: | @@ -96,8 +96,9 @@ static void s390_cpu_reset(CPUState *s, cpu_reset_type type) | S390CPU *cpu = S390_CPU(s); | S390CPUClass *scc = S390_CPU_GET_CLASS(cpu); | CPUS390XState *env = &cpu->env; |+ DeviceState *dev = DEVICE(s); | |- scc->parent_reset(s); |+ scc->parent_reset(dev); | cpu->env.sigp_order = 0; | s390_cpu_set_state(S390_CPU_STATE_STOPPED, cpu); Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20200303100511.5498-1-peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
* target/nios2: Remove MMU_MODE{0,1}_SUFFIXRichard Henderson2020-01-161-2/+0Star
| | | | | | | | | | The functions generated by these macros are unused. Cc: Chris Wulff <crwulff@gmail.com> Cc: Marek Vasut <marex@denx.de> Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* hw/core: Move cpu.c, cpu.h from qom/ to hw/core/Markus Armbruster2019-08-211-1/+1
| | | | | | | | | | Suggested-by: Daniel P. Berrangé <berrange@redhat.com> Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-Id: <20190709152053.16670-2-armbru@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com> [Rebased onto merge commit 95a9457fd44; missed instances of qom/cpu.h in comments replaced]
* Include qemu-common.h exactly where neededMarkus Armbruster2019-06-121-1/+0Star
| | | | | | | | | | | | | | | | No header includes qemu-common.h after this commit, as prescribed by qemu-common.h's file comment. Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-Id: <20190523143508.25387-5-armbru@redhat.com> [Rebased with conflicts resolved automatically, except for include/hw/arm/xlnx-zynqmp.h hw/arm/nrf51_soc.c hw/arm/msf2-soc.c block/qcow2-refcount.c block/qcow2-cluster.c block/qcow2-cache.c target/arm/cpu.h target/lm32/cpu.h target/m68k/cpu.h target/mips/cpu.h target/moxie/cpu.h target/nios2/cpu.h target/openrisc/cpu.h target/riscv/cpu.h target/tilegx/cpu.h target/tricore/cpu.h target/unicore32/cpu.h target/xtensa/cpu.h; bsd-user/main.c and net/tap-bsd.c fixed up]
* cpu: Remove CPU_COMMONRichard Henderson2019-06-101-2/+0Star
| | | | | | | | | | This macro is now always empty, so remove it. This leaves the entire contents of CPUArchState under the control of the guest architecture. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* cpu: Introduce CPUNegativeOffsetStateRichard Henderson2019-06-101-0/+2
| | | | | | | | | Nothing in there so far, but all of the plumbing done within the target ArchCPU state. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* cpu: Move ENV_OFFSET to exec/gen-icount.hRichard Henderson2019-06-101-1/+0Star
| | | | | | | | | Now that we have ArchCPU, we can define this generically, in the one place that needs it. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* target/nios2: Use env_cpu, env_archcpuRichard Henderson2019-06-101-5/+0Star
| | | | | | | | | | | Cleanup in the boilerplate that each target must define. Replace nios2_env_get_cpu with env_archcpu. The combination CPU(nios2_env_get_cpu) should have used ENV_GET_CPU to begin; use env_cpu now. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* cpu: Replace ENV_GET_CPU with env_cpuRichard Henderson2019-06-101-2/+0Star
| | | | | | | | | Now that we have both ArchCPU and CPUArchState, we can define this generically instead of via macro in each target's cpu.h. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Acked-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* cpu: Define ArchCPURichard Henderson2019-06-101-0/+1
| | | | | | | | For all targets, do this just before including exec/cpu-all.h. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Acked-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* cpu: Define CPUArchState with typedefRichard Henderson2019-06-101-3/+2Star
| | | | | | | | For all targets, do this just before including exec/cpu-all.h. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Acked-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* tcg: Split out target/arch/cpu-param.hRichard Henderson2019-06-101-15/+2Star
| | | | | | | | | | | | | | | | For all targets, into this new file move TARGET_LONG_BITS, TARGET_PAGE_BITS, TARGET_PHYS_ADDR_SPACE_BITS, TARGET_VIRT_ADDR_SPACE_BITS, and NB_MMU_MODES. Include this new file from exec/cpu-defs.h. This now removes the somewhat odd requirement that target/arch/cpu.h defines TARGET_LONG_BITS before including exec/cpu-defs.h, so push the bulk of the includes within target/arch/cpu.h to the top. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Acked-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20190510' into stagingPeter Maydell2019-05-161-2/+3
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add CPUClass::tlb_fill. Improve tlb_vaddr_to_host for use by ARM SVE no-fault loads. # gpg: Signature made Fri 10 May 2019 19:48:37 BST # gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F # gpg: issuer "richard.henderson@linaro.org" # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full] # Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F * remotes/rth/tags/pull-tcg-20190510: (27 commits) tcg: Use tlb_fill probe from tlb_vaddr_to_host tcg: Remove CPUClass::handle_mmu_fault tcg: Use CPUClass::tlb_fill in cputlb.c target/xtensa: Convert to CPUClass::tlb_fill target/unicore32: Convert to CPUClass::tlb_fill target/tricore: Convert to CPUClass::tlb_fill target/tilegx: Convert to CPUClass::tlb_fill target/sparc: Convert to CPUClass::tlb_fill target/sh4: Convert to CPUClass::tlb_fill target/s390x: Convert to CPUClass::tlb_fill target/riscv: Convert to CPUClass::tlb_fill target/ppc: Convert to CPUClass::tlb_fill target/openrisc: Convert to CPUClass::tlb_fill target/nios2: Convert to CPUClass::tlb_fill target/moxie: Convert to CPUClass::tlb_fill target/mips: Convert to CPUClass::tlb_fill target/mips: Tidy control flow in mips_cpu_handle_mmu_fault target/mips: Pass a valid error to raise_mmu_exception for user-only target/microblaze: Convert to CPUClass::tlb_fill target/m68k: Convert to CPUClass::tlb_fill ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * target/nios2: Convert to CPUClass::tlb_fillRichard Henderson2019-05-101-2/+3
| | | | | | | | | | | | | | | | | | Remove the leftover debugging cpu_dump_state. Cc: Chris Wulff <crwulff@gmail.com> Cc: Marek Vasut <marex@denx.de> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
* | Clean up header guards that don't match their file nameMarkus Armbruster2019-05-131-3/+4
|/ | | | | | | | | | | | Header guard symbols should match their file name to make guard collisions less likely. Cleaned up with scripts/clean-header-guards.pl, followed by some renaming of new guard symbols picked by the script to better ones. Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-Id: <20190315145123.28030-6-armbru@redhat.com> [Rebase to master: update include/hw/net/ne2000-isa.h]
* Add Nios II semihosting support.Sandra Loosemore2019-04-291-1/+3
| | | | | | | | | | | | This patch adds support for libgloss semihosting to Nios II bare-metal emulation. The specification for the protocol can be found in the libgloss sources. Signed-off-by: Sandra Loosemore <sandra@codesourcery.com> Signed-off-by: Julian Brown <julian@codesourcery.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1554321185-2825-3-git-send-email-sandra@codesourcery.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* qom/cpu: Simplify how CPUClass:cpu_dump_state() printsMarkus Armbruster2019-04-181-2/+1Star
| | | | | | | | | | | | | | | | | | | | CPUClass method dump_statistics() takes an fprintf()-like callback and a FILE * to pass to it. Most callers pass fprintf() and stderr. log_cpu_state() passes fprintf() and qemu_log_file. hmp_info_registers() passes monitor_fprintf() and the current monitor cast to FILE *. monitor_fprintf() casts it right back, and is otherwise identical to monitor_printf(). The callback gets passed around a lot, which is tiresome. The type-punning around monitor_fprintf() is ugly. Drop the callback, and call qemu_fprintf() instead. Also gets rid of the type-punning, since qemu_fprintf() takes NULL instead of the current monitor cast to FILE *. Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Dr. David Alan Gilbert <dgilbert@redhat.com> Message-Id: <20190417191805.28198-15-armbru@redhat.com>
* target: Clean up how the dump_mmu() printMarkus Armbruster2019-04-181-1/+1
| | | | | | | | | | | | | | | | | | | | | The various dump_mmu() take an fprintf()-like callback and a FILE * to pass to it, and so do their helper functions. Passing around callback and argument is rather tiresome. Most dump_mmu() are called only by the target's hmp_info_tlb(). These all pass monitor_printf() cast to fprintf_function and the current monitor cast to FILE *. SPARC's dump_mmu() gets also called from target/sparc/ldst_helper.c a few times #ifdef DEBUG_MMU. These calls pass fprintf() and stdout. The type-punning is technically undefined behaviour, but works in practice. Clean up: drop the callback, and call qemu_printf() instead. Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Dr. David Alan Gilbert <dgilbert@redhat.com> Message-Id: <20190417191805.28198-11-armbru@redhat.com>
* nios2: do not include exec-all.h from cpu.hPaolo Bonzini2018-06-011-1/+0Star
| | | | | | | exec-all.h contains TCG-specific declarations, it should only be includer from helper C files. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* cpu: get rid of unused cpu_init() definesIgor Mammedov2018-03-191-1/+0Star
| | | | | | | | | | | cpu_init(cpu_model) were replaced by cpu_create(cpu_type) so no users are left, remove it. Signed-off-by: Igor Mammedov <imammedo@redhat.com> Acked-by: David Gibson <david@gibson.dropbear.id.au> (ppc) Reviewed-by: Eduardo Habkost <ehabkost@redhat.com> Message-Id: <1518000027-274608-6-git-send-email-imammedo@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
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