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path: root/target/openrisc/cpu.c
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* target/openrisc: Convert to tcg_ops restore_state_to_opcRichard Henderson2022-10-261-0/+13
* accel/tcg: Introduce tb_pc and log_pcRichard Henderson2022-10-041-1/+1
* hw/core: Add CPUClass.get_pcRichard Henderson2022-10-041-0/+8
* target/openrisc: Interrupt handling fixesStafford Horne2022-09-041-1/+0Star
* target/openrisc: Do not reset delay slot flag on early tb exitStafford Horne2022-05-151-0/+11
* target/openrisc: Make openrisc_cpu_tlb_fill sysemu onlyRichard Henderson2021-11-021-1/+1
* target/openrisc: Restrict cpu_exec_interrupt() handler to sysemuPhilippe Mathieu-Daudé2021-09-141-1/+1
* hw/core: Constify TCGCPUOpsRichard Henderson2021-05-271-1/+1
* cpu: Move CPUClass::get_phys_page_debug to SysemuCPUOpsPhilippe Mathieu-Daudé2021-05-271-1/+1
* cpu: Introduce SysemuCPUOps structurePhilippe Mathieu-Daudé2021-05-271-0/+8
* cpu: tcg_ops: move to tcg-cpu-ops.h, keep a pointer in CPUClassClaudio Fontana2021-02-051-4/+13
* cpu: move cc->do_interrupt to tcg_opsClaudio Fontana2021-02-051-1/+1
* cpu: Move tlb_fill to tcg_opsEduardo Habkost2021-02-051-1/+1
* cpu: Move cpu_exec_* to tcg_opsEduardo Habkost2021-02-051-1/+1
* cpu: Introduce TCGCpuOperations structEduardo Habkost2021-02-051-1/+1
* target/openrisc: Move pic_cpu code into CPU object properPeter Maydell2020-12-151-0/+32
* cpu: Use DeviceClass reset instead of a special CPUClass resetPeter Maydell2020-03-181-4/+4
* cpu: Use cpu_class_set_parent_reset()Greg Kurz2020-01-241-2/+1Star
* target/openrisc: Update cpu "any" to v1.3Richard Henderson2019-09-041-1/+1
* target/openrisc: Implement move to/from FPCSRRichard Henderson2019-09-041-0/+1
* target/openrisc: Add support for ORFPX64A32Richard Henderson2019-09-041-1/+1
* target/openrisc: Check CPUCFG_OF32S for float insnsRichard Henderson2019-09-041-1/+1
* target/openrisc: Add VR2 and AVR special processor registersRichard Henderson2019-09-041-2/+6
* target/openrisc: Move VR, UPR, DMMCFGR, IMMCFGR to cpu initRichard Henderson2019-09-041-7/+16
* Include qemu-common.h exactly where neededMarkus Armbruster2019-06-121-1/+0Star
* cpu: Introduce cpu_set_cpustate_pointersRichard Henderson2019-06-101-2/+1Star
* target/openrisc: Convert to CPUClass::tlb_fillRichard Henderson2019-05-101-3/+2Star
* target: Simplify how the TARGET_cpu_list() printMarkus Armbruster2019-04-181-10/+5Star
* target/openrisc: Fix LGPL version numberThomas Huth2019-01-301-1/+1
* linux-user: Implement signals for openriscRichard Henderson2018-07-031-0/+1
* target/openrisc: Increase the TLB sizeRichard Henderson2018-07-021-2/+4
* target/openrisc: Remove indirect function calls for mmuRichard Henderson2018-07-021-4/+0Star
* target/openrisc: Add print_insn_or1kRichard Henderson2018-07-021-0/+6
* target: Do not include "exec/exec-all.h" if it is not necessaryPhilippe Mathieu-Daudé2018-06-011-1/+0Star
* qdev: use device_class_set_parent_realize/unrealize/reset()Philippe Mathieu-Daudé2018-02-051-3/+2Star
* openrisc: cleanup cpu type name compositionIgor Mammedov2017-10-271-46/+23Star
* qom: Introduce CPUClass.tcg_initializeRichard Henderson2017-10-241-6/+1Star
* openrisc/cputimer: Perparation for MulticoreStafford Horne2017-10-201-1/+0Star
* qom/cpu: move cpu_model null check to cpu_class_by_name()Philippe Mathieu-Daudé2017-10-101-4/+0Star
* openrisc: replace cpu_openrisc_init() with cpu_generic_init()Igor Mammedov2017-09-011-5/+0Star
* target/openrisc: Support non-busy idle state using PMR SPRStafford Horne2017-05-041-1/+2
* target/openrisc: Remove duplicate features propertyStafford Horne2017-05-041-14/+3Star
* target/openrisc: implement shadow registersStafford Horne2017-05-041-1/+3
* target/openrisc: Implement EVBAR registerTim 'mithro' Ansell2017-04-211-0/+2
* target/openrisc: Implement lwa, swaRichard Henderson2017-02-131-0/+1
* qom/cpu: move tlb_flush to cpu_common_resetAlex Bennée2017-01-131-8/+1Star
* Move target-* CPU file into a target/ folderThomas Huth2016-12-201-0/+278
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