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path: root/target/openrisc/cpu.h
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* target/openrisc: Make openrisc_cpu_tlb_fill sysemu onlyRichard Henderson2021-11-021-3/+4
* include/exec: Move cpu_signal_handler declarationRichard Henderson2021-09-221-2/+0Star
* target/openrisc: Restrict cpu_exec_interrupt() handler to sysemuPhilippe Mathieu-Daudé2021-09-141-2/+3
* target/openrisc: Move pic_cpu code into CPU object properPeter Maydell2020-12-151-1/+0Star
* qom: Remove module_obj_name parameter from OBJECT_DECLARE* macrosEduardo Habkost2020-09-181-1/+1
* Use OBJECT_DECLARE_TYPE where possibleEduardo Habkost2020-09-091-4/+2Star
* Use DECLARE_*CHECKER* macrosEduardo Habkost2020-09-091-6/+2Star
* Move QOM typedefs and add missing includesEduardo Habkost2020-09-091-4/+7
* Merge remote-tracking branch 'remotes/ehabkost/tags/x86-and-machine-pull-requ...Peter Maydell2020-03-191-1/+1
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| * cpu: Use DeviceClass reset instead of a special CPUClass resetPeter Maydell2020-03-181-1/+1
* | gdbstub: extend GByteArray to read register helpersAlex Bennée2020-03-171-1/+1
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* target/openrisc: Implement move to/from FPCSRRichard Henderson2019-09-041-0/+2
* target/openrisc: Add VR2 and AVR special processor registersRichard Henderson2019-09-041-4/+7
* target/openrisc: Move VR, UPR, DMMCFGR, IMMCFGR to cpu initRichard Henderson2019-09-041-4/+4
* target/openrisc: Make VR and PPC read-onlyRichard Henderson2019-09-041-3/+0Star
* hw/core: Move cpu.c, cpu.h from qom/ to hw/core/Markus Armbruster2019-08-211-1/+1
* migration: Move the VMStateDescription typedef to typedefs.hMarkus Armbruster2019-08-161-1/+1
* Include qemu-common.h exactly where neededMarkus Armbruster2019-06-121-1/+0Star
* cpu: Remove CPU_COMMONRichard Henderson2019-06-101-2/+0Star
* cpu: Introduce CPUNegativeOffsetStateRichard Henderson2019-06-101-1/+1
* cpu: Move ENV_OFFSET to exec/gen-icount.hRichard Henderson2019-06-101-1/+0Star
* target/openrisc: Use env_cpu, env_archcpuRichard Henderson2019-06-101-5/+0Star
* cpu: Replace ENV_GET_CPU with env_cpuRichard Henderson2019-06-101-2/+0Star
* cpu: Define ArchCPURichard Henderson2019-06-101-0/+1
* cpu: Define CPUArchState with typedefRichard Henderson2019-06-101-2/+2
* tcg: Split out target/arch/cpu-param.hRichard Henderson2019-06-101-11/+3Star
* target/openrisc: Convert to CPUClass::tlb_fillRichard Henderson2019-05-101-2/+3
* target/openrisc: Fix LGPL information in the file headersThomas Huth2019-05-081-1/+1
* qom/cpu: Simplify how CPUClass:cpu_dump_state() printsMarkus Armbruster2019-04-181-2/+1Star
* target: Simplify how the TARGET_cpu_list() printMarkus Armbruster2019-04-181-1/+1
* target/openrisc: Reorg tlb lookupRichard Henderson2018-07-031-8/+0Star
* target/openrisc: Increase the TLB sizeRichard Henderson2018-07-021-1/+1
* target/openrisc: Use identical sizes for ITLB and DTLBRichard Henderson2018-07-021-6/+4Star
* target/openrisc: Fix cpu_mmu_indexRichard Henderson2018-07-021-8/+15
* target/openrisc: Reduce tlb to a single dimensionRichard Henderson2018-07-021-4/+2Star
* target/openrisc: Remove indirect function calls for mmuRichard Henderson2018-07-021-11/+0Star
* target/openrisc: Merge tlb allocation into CPUOpenRISCStateRichard Henderson2018-07-021-2/+4
* target/openrisc: Add print_insn_or1kRichard Henderson2018-07-021-0/+1
* cpu: get rid of unused cpu_init() definesIgor Mammedov2018-03-191-2/+0Star
* cpu: add CPU_RESOLVING_TYPE macroIgor Mammedov2018-03-191-0/+1
* target/*/cpu.h: remove softfloat.hAlex Bennée2018-02-211-1/+0Star
* accel/tcg: add size paremeter in tlb_fill()Laurent Vivier2018-01-251-1/+1
* openrisc: cleanup cpu type name compositionIgor Mammedov2017-10-271-0/+3
* openrisc/cputimer: Perparation for MulticoreStafford Horne2017-10-201-1/+3
* openrisc: replace cpu_openrisc_init() with cpu_generic_init()Igor Mammedov2017-09-011-3/+1Star
* target/openrisc: Support non-busy idle state using PMR SPRStafford Horne2017-05-041-0/+10
* target/openrisc: Remove duplicate features propertyStafford Horne2017-05-041-14/+2Star
* target/openrisc: implement shadow registersStafford Horne2017-05-041-2/+13
* target/openrisc: Implement EVBAR registerTim 'mithro' Ansell2017-04-211-0/+7
* target/openrisc: Optimize for r0 being zeroRichard Henderson2017-02-131-1/+4
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