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path: root/target/openrisc/translate.c
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* target/openrisc: Fix LGPL version numberThomas Huth2019-01-301-1/+1
* decodetree: Remove "insn" argument from trans_* expandersRichard Henderson2018-10-311-100/+100
* target/openrisc: Fix cpu_mmu_indexRichard Henderson2018-07-021-1/+1
* target/openrisc: Form the spr index from tcgRichard Henderson2018-07-021-7/+9
* target/openrisc: Exit the TB after l.mtsprRichard Henderson2018-07-021-1/+16
* target/openrisc: Split out is_userRichard Henderson2018-07-021-15/+12Star
* target/openrisc: Link more translation blocksRichard Henderson2018-07-021-41/+55
* target/openrisc: Fix singlestep_enabledRichard Henderson2018-07-021-18/+17Star
* target/openrisc: Use exit_tb instead of CPU_INTERRUPT_EXITTBRichard Henderson2018-07-021-3/+3
* target/openrisc: Remove DISAS_JUMP & DISAS_TB_JUMPRichard Henderson2018-07-021-4/+0Star
* target/openrisc: Add print_insn_or1kRichard Henderson2018-07-021-114/+0Star
* tcg: Pass tb and index to tcg_gen_exit_tb separatelyRichard Henderson2018-06-021-3/+3
* target/openrisc: Merge disas_openrisc_insnRichard Henderson2018-05-141-9/+4Star
* target/openrisc: Convert dec_floatRichard Henderson2018-05-141-230/+128Star
* target/openrisc: Convert dec_compiRichard Henderson2018-05-141-58/+58
* target/openrisc: Convert dec_compRichard Henderson2018-05-141-62/+58Star
* target/openrisc: Convert dec_MRichard Henderson2018-05-141-28/+13Star
* target/openrisc: Convert dec_logicRichard Henderson2018-05-141-36/+26Star
* target/openrisc: Convert dec_macRichard Henderson2018-05-141-33/+22Star
* target/openrisc: Convert dec_calcRichard Henderson2018-05-141-149/+173
* target/openrisc: Convert remainder of dec_misc insnsRichard Henderson2018-05-141-149/+110Star
* target/openrisc: Convert memory insnsRichard Henderson2018-05-141-139/+136Star
* target/openrisc: Convert branch insnsRichard Henderson2018-05-141-78/+72Star
* target/openrisc: Start conversion to decodetree.pyRichard Henderson2018-05-141-43/+41Star
* target-openrisc: Write back result before FPE exceptionRichard Henderson2018-05-141-36/+65
* target/openrisc: convert to TranslatorOpsEmilio G. Cota2018-05-091-84/+79Star
* target/openrisc: convert to DisasContextBaseEmilio G. Cota2018-05-091-47/+46Star
* Merge remote-tracking branch 'remotes/rth/tags/pull-dis-20171026' into stagingPeter Maydell2017-10-271-1/+1
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| * disas: Remove unused flags argumentsRichard Henderson2017-10-251-1/+1
* | tcg: Initialize cpu_env genericallyRichard Henderson2017-10-241-3/+0Star
* | tcg: define tcg_init_ctx and make tcg_ctx a pointerEmilio G. Cota2017-10-241-1/+1
* | tcg: convert tb->cflags reads to tb_cflags(tb)Emilio G. Cota2017-10-241-3/+3
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* target: [tcg] Use a generic enum for DISAS_ valuesLluís Vilanova2017-09-061-0/+6
* tcg: Pass generic CPUState to gen_intermediate_code()Lluís Vilanova2017-07-191-2/+2
* target/openrisc: implement shadow registersStafford Horne2017-05-041-2/+3
* target/openrisc: Optimize for r0 being zeroRichard Henderson2017-02-131-22/+61
* target/openrisc: Tidy handling of delayed branchesRichard Henderson2017-02-131-24/+16Star
* target/openrisc: Tidy ppc/npc implementationRichard Henderson2017-02-131-18/+11Star
* target/openrisc: Optimize l.jal to nextRichard Henderson2017-02-131-1/+5
* target/openrisc: Fix maddRichard Henderson2017-02-131-9/+4Star
* target/openrisc: Implement muld, muldu, macu, msbuRichard Henderson2017-02-131-0/+108
* target/openrisc: Represent MACHI:MACLO as a single unitRichard Henderson2017-02-131-57/+63
* target/openrisc: Implement msyncRichard Henderson2017-02-131-0/+1
* target/openrisc: Enable trap, csync, msync, psync for user modeRichard Henderson2017-02-131-32/+0Star
* target/openrisc: Use movcond where appropriateRichard Henderson2017-02-131-14/+14
* target/openrisc: Keep SR_CY and SR_OV in a separate variablesRichard Henderson2017-02-131-79/+40Star
* target/openrisc: Keep SR_F in a separate variableRichard Henderson2017-02-131-64/+40Star
* target/openrisc: Invert the decoding in dec_calcRichard Henderson2017-02-131-207/+95Star
* target/openrisc: Put SR[OVE] in TB flagsRichard Henderson2017-02-131-9/+15
* target/openrisc: Streamline arithmetic and OVERichard Henderson2017-02-131-249/+177Star