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spice_video_codecs
Experimental fork of QEMU with video encoding patches
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path:
root
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target
/
openrisc
/
translate.c
Commit message (
Expand
)
Author
Age
Files
Lines
*
target/openrisc: Fix LGPL version number
Thomas Huth
2019-01-30
1
-1
/
+1
*
decodetree: Remove "insn" argument from trans_* expanders
Richard Henderson
2018-10-31
1
-100
/
+100
*
target/openrisc: Fix cpu_mmu_index
Richard Henderson
2018-07-02
1
-1
/
+1
*
target/openrisc: Form the spr index from tcg
Richard Henderson
2018-07-02
1
-7
/
+9
*
target/openrisc: Exit the TB after l.mtspr
Richard Henderson
2018-07-02
1
-1
/
+16
*
target/openrisc: Split out is_user
Richard Henderson
2018-07-02
1
-15
/
+12
*
target/openrisc: Link more translation blocks
Richard Henderson
2018-07-02
1
-41
/
+55
*
target/openrisc: Fix singlestep_enabled
Richard Henderson
2018-07-02
1
-18
/
+17
*
target/openrisc: Use exit_tb instead of CPU_INTERRUPT_EXITTB
Richard Henderson
2018-07-02
1
-3
/
+3
*
target/openrisc: Remove DISAS_JUMP & DISAS_TB_JUMP
Richard Henderson
2018-07-02
1
-4
/
+0
*
target/openrisc: Add print_insn_or1k
Richard Henderson
2018-07-02
1
-114
/
+0
*
tcg: Pass tb and index to tcg_gen_exit_tb separately
Richard Henderson
2018-06-02
1
-3
/
+3
*
target/openrisc: Merge disas_openrisc_insn
Richard Henderson
2018-05-14
1
-9
/
+4
*
target/openrisc: Convert dec_float
Richard Henderson
2018-05-14
1
-230
/
+128
*
target/openrisc: Convert dec_compi
Richard Henderson
2018-05-14
1
-58
/
+58
*
target/openrisc: Convert dec_comp
Richard Henderson
2018-05-14
1
-62
/
+58
*
target/openrisc: Convert dec_M
Richard Henderson
2018-05-14
1
-28
/
+13
*
target/openrisc: Convert dec_logic
Richard Henderson
2018-05-14
1
-36
/
+26
*
target/openrisc: Convert dec_mac
Richard Henderson
2018-05-14
1
-33
/
+22
*
target/openrisc: Convert dec_calc
Richard Henderson
2018-05-14
1
-149
/
+173
*
target/openrisc: Convert remainder of dec_misc insns
Richard Henderson
2018-05-14
1
-149
/
+110
*
target/openrisc: Convert memory insns
Richard Henderson
2018-05-14
1
-139
/
+136
*
target/openrisc: Convert branch insns
Richard Henderson
2018-05-14
1
-78
/
+72
*
target/openrisc: Start conversion to decodetree.py
Richard Henderson
2018-05-14
1
-43
/
+41
*
target-openrisc: Write back result before FPE exception
Richard Henderson
2018-05-14
1
-36
/
+65
*
target/openrisc: convert to TranslatorOps
Emilio G. Cota
2018-05-09
1
-84
/
+79
*
target/openrisc: convert to DisasContextBase
Emilio G. Cota
2018-05-09
1
-47
/
+46
*
Merge remote-tracking branch 'remotes/rth/tags/pull-dis-20171026' into staging
Peter Maydell
2017-10-27
1
-1
/
+1
|
\
|
*
disas: Remove unused flags arguments
Richard Henderson
2017-10-25
1
-1
/
+1
*
|
tcg: Initialize cpu_env generically
Richard Henderson
2017-10-24
1
-3
/
+0
*
|
tcg: define tcg_init_ctx and make tcg_ctx a pointer
Emilio G. Cota
2017-10-24
1
-1
/
+1
*
|
tcg: convert tb->cflags reads to tb_cflags(tb)
Emilio G. Cota
2017-10-24
1
-3
/
+3
|
/
*
target: [tcg] Use a generic enum for DISAS_ values
Lluís Vilanova
2017-09-06
1
-0
/
+6
*
tcg: Pass generic CPUState to gen_intermediate_code()
Lluís Vilanova
2017-07-19
1
-2
/
+2
*
target/openrisc: implement shadow registers
Stafford Horne
2017-05-04
1
-2
/
+3
*
target/openrisc: Optimize for r0 being zero
Richard Henderson
2017-02-13
1
-22
/
+61
*
target/openrisc: Tidy handling of delayed branches
Richard Henderson
2017-02-13
1
-24
/
+16
*
target/openrisc: Tidy ppc/npc implementation
Richard Henderson
2017-02-13
1
-18
/
+11
*
target/openrisc: Optimize l.jal to next
Richard Henderson
2017-02-13
1
-1
/
+5
*
target/openrisc: Fix madd
Richard Henderson
2017-02-13
1
-9
/
+4
*
target/openrisc: Implement muld, muldu, macu, msbu
Richard Henderson
2017-02-13
1
-0
/
+108
*
target/openrisc: Represent MACHI:MACLO as a single unit
Richard Henderson
2017-02-13
1
-57
/
+63
*
target/openrisc: Implement msync
Richard Henderson
2017-02-13
1
-0
/
+1
*
target/openrisc: Enable trap, csync, msync, psync for user mode
Richard Henderson
2017-02-13
1
-32
/
+0
*
target/openrisc: Use movcond where appropriate
Richard Henderson
2017-02-13
1
-14
/
+14
*
target/openrisc: Keep SR_CY and SR_OV in a separate variables
Richard Henderson
2017-02-13
1
-79
/
+40
*
target/openrisc: Keep SR_F in a separate variable
Richard Henderson
2017-02-13
1
-64
/
+40
*
target/openrisc: Invert the decoding in dec_calc
Richard Henderson
2017-02-13
1
-207
/
+95
*
target/openrisc: Put SR[OVE] in TB flags
Richard Henderson
2017-02-13
1
-9
/
+15
*
target/openrisc: Streamline arithmetic and OVE
Richard Henderson
2017-02-13
1
-249
/
+177
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