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path: root/target/openrisc/translate.c
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* meson: targetPaolo Bonzini2020-08-211-1/+1
* meson: rename included C source files to .c.incPaolo Bonzini2020-08-211-1/+1
* tcg: Search includes from the project root source directoryPhilippe Mathieu-Daudé2020-01-161-1/+1
* target/openrisc: fetch code with translator_ldEmilio G. Cota2019-10-281-1/+1
* target/openrisc: Implement l.adrpRichard Henderson2019-09-041-0/+13
* target/openrisc: Implement unordered fp comparisonsRichard Henderson2019-09-041-0/+85
* target/openrisc: Add support for ORFPX64A32Richard Henderson2019-09-041-0/+230
* target/openrisc: Check CPUCFG_OF32S for float insnsRichard Henderson2019-09-041-49/+35Star
* target/openrisc: Cache R0 in DisasContextRichard Henderson2019-09-041-7/+12
* target/openrisc: Replace cpu register array with a functionRichard Henderson2019-09-041-97/+116
* target/openrisc: Add DisasContext parameter to check_r0_writeRichard Henderson2019-09-041-47/+49
* tcg: TCGMemOp is now accelerator independent MemOpTony Nguyen2019-09-031-2/+2
* Include qemu-common.h exactly where neededMarkus Armbruster2019-06-121-1/+0Star
* tcg: Hoist max_insns computation to tb_gen_codeRichard Henderson2019-04-241-2/+2
* qom/cpu: Simplify how CPUClass:cpu_dump_state() printsMarkus Armbruster2019-04-181-6/+5Star
* target/openrisc: Fix LGPL version numberThomas Huth2019-01-301-1/+1
* decodetree: Remove "insn" argument from trans_* expandersRichard Henderson2018-10-311-100/+100
* target/openrisc: Fix cpu_mmu_indexRichard Henderson2018-07-021-1/+1
* target/openrisc: Form the spr index from tcgRichard Henderson2018-07-021-7/+9
* target/openrisc: Exit the TB after l.mtsprRichard Henderson2018-07-021-1/+16
* target/openrisc: Split out is_userRichard Henderson2018-07-021-15/+12Star
* target/openrisc: Link more translation blocksRichard Henderson2018-07-021-41/+55
* target/openrisc: Fix singlestep_enabledRichard Henderson2018-07-021-18/+17Star
* target/openrisc: Use exit_tb instead of CPU_INTERRUPT_EXITTBRichard Henderson2018-07-021-3/+3
* target/openrisc: Remove DISAS_JUMP & DISAS_TB_JUMPRichard Henderson2018-07-021-4/+0Star
* target/openrisc: Add print_insn_or1kRichard Henderson2018-07-021-114/+0Star
* tcg: Pass tb and index to tcg_gen_exit_tb separatelyRichard Henderson2018-06-021-3/+3
* target/openrisc: Merge disas_openrisc_insnRichard Henderson2018-05-141-9/+4Star
* target/openrisc: Convert dec_floatRichard Henderson2018-05-141-230/+128Star
* target/openrisc: Convert dec_compiRichard Henderson2018-05-141-58/+58
* target/openrisc: Convert dec_compRichard Henderson2018-05-141-62/+58Star
* target/openrisc: Convert dec_MRichard Henderson2018-05-141-28/+13Star
* target/openrisc: Convert dec_logicRichard Henderson2018-05-141-36/+26Star
* target/openrisc: Convert dec_macRichard Henderson2018-05-141-33/+22Star
* target/openrisc: Convert dec_calcRichard Henderson2018-05-141-149/+173
* target/openrisc: Convert remainder of dec_misc insnsRichard Henderson2018-05-141-149/+110Star
* target/openrisc: Convert memory insnsRichard Henderson2018-05-141-139/+136Star
* target/openrisc: Convert branch insnsRichard Henderson2018-05-141-78/+72Star
* target/openrisc: Start conversion to decodetree.pyRichard Henderson2018-05-141-43/+41Star
* target-openrisc: Write back result before FPE exceptionRichard Henderson2018-05-141-36/+65
* target/openrisc: convert to TranslatorOpsEmilio G. Cota2018-05-091-84/+79Star
* target/openrisc: convert to DisasContextBaseEmilio G. Cota2018-05-091-47/+46Star
* Merge remote-tracking branch 'remotes/rth/tags/pull-dis-20171026' into stagingPeter Maydell2017-10-271-1/+1
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| * disas: Remove unused flags argumentsRichard Henderson2017-10-251-1/+1
* | tcg: Initialize cpu_env genericallyRichard Henderson2017-10-241-3/+0Star
* | tcg: define tcg_init_ctx and make tcg_ctx a pointerEmilio G. Cota2017-10-241-1/+1
* | tcg: convert tb->cflags reads to tb_cflags(tb)Emilio G. Cota2017-10-241-3/+3
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* target: [tcg] Use a generic enum for DISAS_ valuesLluís Vilanova2017-09-061-0/+6
* tcg: Pass generic CPUState to gen_intermediate_code()Lluís Vilanova2017-07-191-2/+2
* target/openrisc: implement shadow registersStafford Horne2017-05-041-2/+3
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