bwlp/qemu.git - Experimental fork of QEMU with video encoding patches

	Commit message (Expand)	Author	Age	Files	Lines
*	meson: target	Paolo Bonzini	2020-08-21	1	-1/+1
*	meson: rename included C source files to .c.inc	Paolo Bonzini	2020-08-21	1	-1/+1
*	tcg: Search includes from the project root source directory	Philippe Mathieu-Daudé	2020-01-16	1	-1/+1
*	target/openrisc: fetch code with translator_ld	Emilio G. Cota	2019-10-28	1	-1/+1
*	target/openrisc: Implement l.adrp	Richard Henderson	2019-09-04	1	-0/+13
*	target/openrisc: Implement unordered fp comparisons	Richard Henderson	2019-09-04	1	-0/+85
*	target/openrisc: Add support for ORFPX64A32	Richard Henderson	2019-09-04	1	-0/+230
*	target/openrisc: Check CPUCFG_OF32S for float insns	Richard Henderson	2019-09-04	1	-49/+35
*	target/openrisc: Cache R0 in DisasContext	Richard Henderson	2019-09-04	1	-7/+12
*	target/openrisc: Replace cpu register array with a function	Richard Henderson	2019-09-04	1	-97/+116
*	target/openrisc: Add DisasContext parameter to check_r0_write	Richard Henderson	2019-09-04	1	-47/+49
*	tcg: TCGMemOp is now accelerator independent MemOp	Tony Nguyen	2019-09-03	1	-2/+2
*	Include qemu-common.h exactly where needed	Markus Armbruster	2019-06-12	1	-1/+0
*	tcg: Hoist max_insns computation to tb_gen_code	Richard Henderson	2019-04-24	1	-2/+2
*	qom/cpu: Simplify how CPUClass:cpu_dump_state() prints	Markus Armbruster	2019-04-18	1	-6/+5
*	target/openrisc: Fix LGPL version number	Thomas Huth	2019-01-30	1	-1/+1
*	decodetree: Remove "insn" argument from trans_* expanders	Richard Henderson	2018-10-31	1	-100/+100
*	target/openrisc: Fix cpu_mmu_index	Richard Henderson	2018-07-02	1	-1/+1
*	target/openrisc: Form the spr index from tcg	Richard Henderson	2018-07-02	1	-7/+9
*	target/openrisc: Exit the TB after l.mtspr	Richard Henderson	2018-07-02	1	-1/+16
*	target/openrisc: Split out is_user	Richard Henderson	2018-07-02	1	-15/+12
*	target/openrisc: Link more translation blocks	Richard Henderson	2018-07-02	1	-41/+55
*	target/openrisc: Fix singlestep_enabled	Richard Henderson	2018-07-02	1	-18/+17
*	target/openrisc: Use exit_tb instead of CPU_INTERRUPT_EXITTB	Richard Henderson	2018-07-02	1	-3/+3
*	target/openrisc: Remove DISAS_JUMP & DISAS_TB_JUMP	Richard Henderson	2018-07-02	1	-4/+0
*	target/openrisc: Add print_insn_or1k	Richard Henderson	2018-07-02	1	-114/+0
*	tcg: Pass tb and index to tcg_gen_exit_tb separately	Richard Henderson	2018-06-02	1	-3/+3
*	target/openrisc: Merge disas_openrisc_insn	Richard Henderson	2018-05-14	1	-9/+4
*	target/openrisc: Convert dec_float	Richard Henderson	2018-05-14	1	-230/+128
*	target/openrisc: Convert dec_compi	Richard Henderson	2018-05-14	1	-58/+58
*	target/openrisc: Convert dec_comp	Richard Henderson	2018-05-14	1	-62/+58
*	target/openrisc: Convert dec_M	Richard Henderson	2018-05-14	1	-28/+13
*	target/openrisc: Convert dec_logic	Richard Henderson	2018-05-14	1	-36/+26
*	target/openrisc: Convert dec_mac	Richard Henderson	2018-05-14	1	-33/+22
*	target/openrisc: Convert dec_calc	Richard Henderson	2018-05-14	1	-149/+173
*	target/openrisc: Convert remainder of dec_misc insns	Richard Henderson	2018-05-14	1	-149/+110
*	target/openrisc: Convert memory insns	Richard Henderson	2018-05-14	1	-139/+136
*	target/openrisc: Convert branch insns	Richard Henderson	2018-05-14	1	-78/+72
*	target/openrisc: Start conversion to decodetree.py	Richard Henderson	2018-05-14	1	-43/+41
*	target-openrisc: Write back result before FPE exception	Richard Henderson	2018-05-14	1	-36/+65
*	target/openrisc: convert to TranslatorOps	Emilio G. Cota	2018-05-09	1	-84/+79
*	target/openrisc: convert to DisasContextBase	Emilio G. Cota	2018-05-09	1	-47/+46
*	Merge remote-tracking branch 'remotes/rth/tags/pull-dis-20171026' into staging	Peter Maydell	2017-10-27	1	-1/+1
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\| *	disas: Remove unused flags arguments	Richard Henderson	2017-10-25	1	-1/+1
* \|	tcg: Initialize cpu_env generically	Richard Henderson	2017-10-24	1	-3/+0
* \|	tcg: define tcg_init_ctx and make tcg_ctx a pointer	Emilio G. Cota	2017-10-24	1	-1/+1
* \|	tcg: convert tb->cflags reads to tb_cflags(tb)	Emilio G. Cota	2017-10-24	1	-3/+3
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*	target: [tcg] Use a generic enum for DISAS_ values	Lluís Vilanova	2017-09-06	1	-0/+6
*	tcg: Pass generic CPUState to gen_intermediate_code()	Lluís Vilanova	2017-07-19	1	-2/+2
*	target/openrisc: implement shadow registers	Stafford Horne	2017-05-04	1	-2/+3