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path: root/target/riscv/cpu.c
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* target/riscv: setup everything for rv64 to support rv128 executionFrédéric Pétrot2022-01-081-0/+20
* target/riscv: array for the 64 upper bits of 128-bit registersFrédéric Pétrot2022-01-081-0/+9
* target/riscv: Fix position of 'experimental' commentPhilipp Tomsich2022-01-081-1/+2
* target/riscv: Enable the Hypervisor extension by defaultAlistair Francis2022-01-081-1/+1
* target/riscv: Mark the Hypervisor extension as non experimentalAlistair Francis2022-01-081-1/+1
* target/riscv: Enable bitmanip Zb[abcs] instructionsVineet Gupta2021-12-201-4/+4
* target/riscv: gdb: support vector registers for rv64 & rv32Hsiangkai Wang2021-12-201-0/+2
* target/riscv: drop vector 0.7.1 and add 1.0 supportFrank Chang2021-12-201-8/+8
* target/riscv: zfh: add Zfhmin cpu propertyFrank Chang2021-12-201-0/+1
* target/riscv: zfh: add Zfh cpu propertyFrank Chang2021-12-201-0/+1
* target/riscv: Make riscv_cpu_tlb_fill sysemu onlyRichard Henderson2021-11-021-1/+1
* target/riscv: Allow experimental J-ext to be turned onAlexey Baturo2021-10-281-0/+4
* target/riscv: Print new PM CSRs in QEMU logsAlexey Baturo2021-10-281-0/+7
* target/riscv: Support CSRs required for RISC-V PM extension except for the h-...Alexey Baturo2021-10-281-0/+2
* target/riscv: Use riscv_csrrw_debug for cpu_dumpRichard Henderson2021-10-221-44/+45
* target/riscv: Add MXL/SXL/UXL to TB_FLAGSRichard Henderson2021-10-211-0/+8
* target/riscv: Replace riscv_cpu_is_32bit with riscv_cpu_mxlRichard Henderson2021-10-211-10/+14
* target/riscv: Split misa.mxl and misa.extRichard Henderson2021-10-211-33/+45
* target/riscv: Organise the CPU propertiesAlistair Francis2021-10-211-7/+10
* target/riscv: line up all of the registers in the info register dumpTravis Geiselbrecht2021-10-211-5/+5
* target/riscv: Remove RVB (replaced by Zb[abcs])Philipp Tomsich2021-10-071-26/+0Star
* target/riscv: Add x-zba, x-zbb, x-zbc and x-zbs propertiesPhilipp Tomsich2021-10-071-0/+4
* target/riscv: Expose interrupt pending bits as GPIO linesAlistair Francis2021-09-201-0/+30
* target/riscv: Update the ePMP CSR addressAlistair Francis2021-09-201-0/+1
* target/riscv: Restrict cpu_exec_interrupt() handler to sysemuPhilippe Mathieu-Daudé2021-09-141-1/+1
* target/riscv: Don't wrongly override isa versionLIU Zhiwei2021-09-011-6/+8
* target/riscv: rvb: add b-ext version cpu optionFrank Chang2021-06-081-0/+23
* target/riscv: rvb: support and turn on B-extension from command lineKito Cheng2021-06-081-0/+4
* target/riscv: Dump CSR mscratch/sscratch/satpChangbin Du2021-06-081-2/+5
* target/riscv: Remove unnecessary riscv_*_names[] declarationBin Meng2021-06-081-2/+2
* hw/core: Constify TCGCPUOpsRichard Henderson2021-05-271-1/+1
* cpu: Move CPUClass::get_phys_page_debug to SysemuCPUOpsPhilippe Mathieu-Daudé2021-05-271-1/+1
* cpu: Move CPUClass::write_elf* to SysemuCPUOpsPhilippe Mathieu-Daudé2021-05-271-2/+2
* cpu: Move CPUClass::vmsd to SysemuCPUOpsPhilippe Mathieu-Daudé2021-05-271-1/+1
* cpu: Introduce SysemuCPUOps structurePhilippe Mathieu-Daudé2021-05-271-0/+8
* cpu: Rename CPUClass vmsd -> legacy_vmsdPhilippe Mathieu-Daudé2021-05-271-2/+1Star
* target/riscv: Remove the hardcoded RVXLEN macroAlistair Francis2021-05-111-1/+5
* target/riscv: fix a typo with interrupt namesEmmanuel Blot2021-05-111-1/+1
* target/riscv: Add ePMP support for the Ibex CPUAlistair Francis2021-05-111-0/+1
* target/riscv: Add a config option for ePMPHou Weiying2021-05-111-0/+10
* target/riscv: Convert the RISC-V exceptions to an enumAlistair Francis2021-05-111-1/+1
* target/riscv: Add Shakti C class CPUVijai Kumar K2021-05-111-0/+1
* target/riscv: Align the data type of reset vector addressDylan Jhong2021-05-111-1/+1
* target/riscv: Remove privilege v1.9 specific CSR related codeAtish Patra2021-05-111-1/+1
* target/riscv: Add proper two-stage lookup exception detectionGeorg Kotheimer2021-03-231-0/+1
* Various spelling fixesMichael Tokarev2021-03-091-1/+1
* target-riscv: support QMP dump-guest-memoryYifei Jiang2021-03-041-0/+2
* cpu: tcg_ops: move to tcg-cpu-ops.h, keep a pointer in CPUClassClaudio Fontana2021-02-051-7/+16
* cpu: move do_unaligned_access to tcg_opsClaudio Fontana2021-02-051-1/+1
* cpu: move cc->transaction_failed to tcg_opsClaudio Fontana2021-02-051-1/+1
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