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path: root/target/riscv/cpu.h
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* target/riscv: gdb: support vector registers for rv64 & rv32Hsiangkai Wang2021-12-201-0/+1
* target/riscv: rvv-1.0: relax RV_VLEN_MAX to 1024-bitsFrank Chang2021-12-201-1/+1
* target/riscv: rvv-1.0: take fractional LMUL into vector max elements calculationFrank Chang2021-12-201-9/+18
* target/riscv: rvv-1.0: add VMA and VTAFrank Chang2021-12-201-0/+2
* target/riscv: rvv-1.0: add fractional LMULFrank Chang2021-12-201-12/+14
* target/riscv: rvv-1.0: add translation-time vector context statusFrank Chang2021-12-201-2/+3
* target/riscv: rvv-1.0: add mstatus VS fieldLIU Zhiwei2021-12-201-0/+2
* target/riscv: drop vector 0.7.1 and add 1.0 supportFrank Chang2021-12-201-1/+1
* target/riscv: zfh: implement zfhmin extensionFrank Chang2021-12-201-0/+1
* target/riscv: zfh: half-precision load and storeKito Cheng2021-12-201-0/+1
* target/riscv: remove force HS exceptionJose Martins2021-10-291-2/+0Star
* target/riscv: Implement address masking functions required for RISC-V Pointer...Anatoly Parshintsev2021-10-281-0/+2
* target/riscv: Support CSRs required for RISC-V PM extension except for the h-...Alexey Baturo2021-10-281-0/+11
* target/riscv: Add J-extension into RISC-VAlexey Baturo2021-10-281-0/+2
* target/riscv: Add MXL/SXL/UXL to TB_FLAGSRichard Henderson2021-10-211-0/+2
* target/riscv: Replace riscv_cpu_is_32bit with riscv_cpu_mxlRichard Henderson2021-10-211-1/+8
* target/riscv: Split misa.mxl and misa.extRichard Henderson2021-10-211-7/+8
* target/riscv: Move cpu_get_tb_cpu_state out of lineRichard Henderson2021-10-211-45/+2Star
* target/riscv: fix TB_FLAGS bits overlapping bug for rvv/rvhFrank Chang2021-10-211-7/+7
* target/riscv: Set mstatus_hs.[SD|FS] bits if Clean and V=1 in mark_fs_dirty()Frank Chang2021-10-071-0/+4
* target/riscv: Remove RVB (replaced by Zb[abcs])Philipp Tomsich2021-10-071-3/+0Star
* target/riscv: Add x-zba, x-zbb, x-zbc and x-zbs propertiesPhilipp Tomsich2021-10-071-0/+4
* hw/core: Make do_unaligned_access noreturnRichard Henderson2021-09-221-1/+1
* include/exec: Move cpu_signal_handler declarationRichard Henderson2021-09-221-2/+0Star
* target/riscv: Restrict cpu_exec_interrupt() handler to sysemuPhilippe Mathieu-Daudé2021-09-141-1/+1
* target/riscv: rvb: add b-ext version cpu optionFrank Chang2021-06-081-0/+3
* target/riscv: rvb: support and turn on B-extension from command lineKito Cheng2021-06-081-0/+1
* target/riscv: rvb: count leading/trailing zerosKito Cheng2021-06-081-0/+1
* target/riscv: Remove unnecessary riscv_*_names[] declarationBin Meng2021-06-081-2/+0Star
* target/riscv: Do not include 'pmp.h' in user emulationPhilippe Mathieu-Daudé2021-06-081-0/+2
* target/riscv: Remove the hardcoded RVXLEN macroAlistair Francis2021-05-111-6/+0Star
* target/riscv: Add a config option for ePMPHou Weiying2021-05-111-0/+1
* target/riscv: Add ePMP CSR access functionsHou Weiying2021-05-111-0/+1
* target/riscv: Add the ePMP featureAlistair Francis2021-05-111-0/+1
* target/riscv: Use RISCVException enum for CSR accessAlistair Francis2021-05-111-4/+7
* target/riscv: Use the RISCVException enum for CSR operationsAlistair Francis2021-05-111-6/+8
* target/riscv: Use the RISCVException enum for CSR predicatesAlistair Francis2021-05-111-1/+2
* target/riscv: Add Shakti C class CPUVijai Kumar K2021-05-111-0/+1
* target/riscv: Remove privilege v1.9 specific CSR related codeAtish Patra2021-05-111-3/+1Star
* target/riscv: Add proper two-stage lookup exception detectionGeorg Kotheimer2021-03-231-0/+4
* target-riscv: support QMP dump-guest-memoryYifei Jiang2021-03-041-0/+4
* target/riscv: Declare csr_ops[] with a known sizeBin Meng2021-03-041-1/+1
* target/riscv: Generate the GDB XML file for CSR registers dynamicallyBin Meng2021-01-161-0/+2
* target/riscv: Add CSR name in the CSR function tableBin Meng2021-01-161-0/+1
* target/riscv: Make csr_ops[CSR_TABLE_SIZE] externalBin Meng2021-01-161-0/+8
* target/riscv: Add a riscv_cpu_is_32bit() helper functionAlistair Francis2020-12-181-0/+2
* target/riscv: Add a TYPE_RISCV_CPU_BASE CPUAlistair Francis2020-12-181-0/+6
* target/riscv: Remove the hyp load and store functionsAlistair Francis2020-11-101-0/+12
* target/riscv: Remove the HS_TWO_STAGE flagAlistair Francis2020-11-101-2/+1Star
* target/riscv: Add a virtualised MMU ModeAlistair Francis2020-11-101-1/+3
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