| Commit message (Expand) | Author | Age | Files | Lines |
* | target-riscv: support QMP dump-guest-memory | Yifei Jiang | 2021-03-04 | 1 | -0/+4 |
* | target/riscv: Declare csr_ops[] with a known size | Bin Meng | 2021-03-04 | 1 | -1/+1 |
* | target/riscv: Generate the GDB XML file for CSR registers dynamically | Bin Meng | 2021-01-16 | 1 | -0/+2 |
* | target/riscv: Add CSR name in the CSR function table | Bin Meng | 2021-01-16 | 1 | -0/+1 |
* | target/riscv: Make csr_ops[CSR_TABLE_SIZE] external | Bin Meng | 2021-01-16 | 1 | -0/+8 |
* | target/riscv: Add a riscv_cpu_is_32bit() helper function | Alistair Francis | 2020-12-18 | 1 | -0/+2 |
* | target/riscv: Add a TYPE_RISCV_CPU_BASE CPU | Alistair Francis | 2020-12-18 | 1 | -0/+6 |
* | target/riscv: Remove the hyp load and store functions | Alistair Francis | 2020-11-10 | 1 | -0/+12 |
* | target/riscv: Remove the HS_TWO_STAGE flag | Alistair Francis | 2020-11-10 | 1 | -2/+1 |
* | target/riscv: Add a virtualised MMU Mode | Alistair Francis | 2020-11-10 | 1 | -1/+3 |
* | target/riscv: Merge m/vsstatus and m/vsstatush into one uint64_t unit | Yifei Jiang | 2020-11-03 | 1 | -13/+11 |
* | target/riscv: raise exception to HS-mode at get_physical_address | Yifei Jiang | 2020-10-22 | 1 | -3/+7 |
* | qom: Remove module_obj_name parameter from OBJECT_DECLARE* macros | Eduardo Habkost | 2020-09-18 | 1 | -1/+1 |
* | Merge remote-tracking branch 'remotes/alistair/tags/pull-riscv-to-apply-20200... | Peter Maydell | 2020-09-13 | 1 | -2/+6 |
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| * | hw/riscv: clint: Avoid using hard-coded timebase frequency | Bin Meng | 2020-09-10 | 1 | -2/+4 |
| * | target/riscv: cpu: Add a new 'resetvec' property | Bin Meng | 2020-09-10 | 1 | -0/+1 |
| * | target/riscv: Fix bug in getting trap cause name for trace_riscv_trap | Yifei Jiang | 2020-09-10 | 1 | -0/+1 |
* | | Use OBJECT_DECLARE_TYPE where possible | Eduardo Habkost | 2020-09-09 | 1 | -4/+2 |
* | | Use DECLARE_*CHECKER* macros | Eduardo Habkost | 2020-09-09 | 1 | -6/+2 |
* | | Move QOM typedefs and add missing includes | Eduardo Habkost | 2020-09-09 | 1 | -4/+7 |
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* | target/riscv: Allow setting a two-stage lookup in the virt status | Alistair Francis | 2020-08-25 | 1 | -0/+2 |
* | target/riscv: fix vill bit index in vtype register | Frank Chang | 2020-07-14 | 1 | -1/+1 |
* | target/riscv: configure and turn on vector extension from command line | LIU Zhiwei | 2020-07-02 | 1 | -1/+3 |
* | target/riscv: add vector configure instruction | LIU Zhiwei | 2020-07-02 | 1 | -9/+54 |
* | target/riscv: implementation-defined constant parameters | LIU Zhiwei | 2020-07-02 | 1 | -0/+5 |
* | target/riscv: add vector extension field in CPURISCVState | LIU Zhiwei | 2020-07-02 | 1 | -0/+12 |
* | target/riscv: Add the lowRISC Ibex CPU | Alistair Francis | 2020-06-03 | 1 | -0/+1 |
* | target/riscv: Drop support for ISA spec version 1.09.1 | Alistair Francis | 2020-06-03 | 1 | -1/+0 |
* | target/riscv: Remove the deprecated CPUs | Alistair Francis | 2020-06-03 | 1 | -7/+0 |
* | target/riscv: Add a sifive-e34 cpu type | Corey Wharton | 2020-04-29 | 1 | -0/+1 |
* | Merge remote-tracking branch 'remotes/ehabkost/tags/x86-and-machine-pull-requ... | Peter Maydell | 2020-03-19 | 1 | -1/+1 |
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| * | cpu: Use DeviceClass reset instead of a special CPUClass reset | Peter Maydell | 2020-03-18 | 1 | -1/+1 |
* | | gdbstub: extend GByteArray to read register helpers | Alex Bennée | 2020-03-17 | 1 | -1/+1 |
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* | target/riscv: Emulate TIME CSRs for privileged mode | Anup Patel | 2020-02-27 | 1 | -0/+5 |
* | target/riscv: Allow enabling the Hypervisor extension | Alistair Francis | 2020-02-27 | 1 | -0/+1 |
* | target/riscv: Add support for the 32-bit MSTATUSH CSR | Alistair Francis | 2020-02-27 | 1 | -0/+10 |
* | target/riscv: Implement second stage MMU | Alistair Francis | 2020-02-27 | 1 | -0/+1 |
* | target/riscv: Only set TB flags with FP status if enabled | Alistair Francis | 2020-02-27 | 1 | -1/+4 |
* | target/riscv: Add virtual register swapping function | Alistair Francis | 2020-02-27 | 1 | -0/+11 |
* | target/riscv: Add the force HS exception mode | Alistair Francis | 2020-02-27 | 1 | -0/+2 |
* | target/riscv: Add the virtulisation mode | Alistair Francis | 2020-02-27 | 1 | -0/+4 |
* | target/riscv: Add the Hypervisor CSRs to CPUState | Alistair Francis | 2020-02-27 | 1 | -0/+21 |
* | target/riscv: Add the Hypervisor extension | Alistair Francis | 2020-02-27 | 1 | -0/+1 |
* | target/riscv: Convert MIP CSR to target_ulong | Alistair Francis | 2020-02-27 | 1 | -1/+1 |
* | target/riscv: Fix tb->flags FS status | ShihPo Hung | 2020-01-16 | 1 | -4/+1 |
* | target/riscv: Remove atomic accesses to MIP CSR | Alistair Francis | 2019-11-14 | 1 | -9/+0 |
* | RISC-V: Implement cpu_do_transaction_failed | Palmer Dabbelt | 2019-10-28 | 1 | -2/+5 |
* | target/riscv: Use TB_FLAGS_MSTATUS_FS for floating point | Alistair Francis | 2019-09-17 | 1 | -1/+1 |
* | target/riscv: Create function to test if FP is enabled | Alistair Francis | 2019-09-17 | 1 | -1/+5 |
* | hw/core: Move cpu.c, cpu.h from qom/ to hw/core/ | Markus Armbruster | 2019-08-21 | 1 | -1/+1 |