summaryrefslogtreecommitdiffstats
path: root/target
Commit message (Expand)AuthorAgeFilesLines
* qtest: delete superfluous inclusions of qtest.hChen Qun2021-03-091-1/+0Star
* Merge remote-tracking branch 'remotes/philmd-gitlab/tags/renesas-20210306' in...Peter Maydell2021-03-082-62/+50Star
|\
| * target/sh4: Remove unused definitionsPhilippe Mathieu-Daudé2021-03-061-11/+0Star
| * target/sh4: Let get_physical_address() use MMUAccessType access_typePhilippe Mathieu-Daudé2021-03-061-10/+10
| * target/sh4: Remove unused 'int access_type' argumentPhilippe Mathieu-Daudé2021-03-061-8/+7Star
| * target/sh4: Replace magic value by MMUAccessType definitionsPhilippe Mathieu-Daudé2021-03-061-8/+8
| * target/sh4: Fix code style for checkpatch.plPhilippe Mathieu-Daudé2021-03-061-41/+41
* | Merge remote-tracking branch 'remotes/bonzini-gitlab/tags/for-upstream' into ...Peter Maydell2021-03-081-2/+7
|\ \
| * | KVM: x86: do not fail if software breakpoint has already been removedPaolo Bonzini2021-03-061-2/+7
* | | Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20210308'...Peter Maydell2021-03-0811-101/+160
|\ \ \ | |_|/ |/| |
| * | target/arm/cpu: Update coding style to make checkpatch.pl happyPhilippe Mathieu-Daudé2021-03-051-4/+8
| * | target/arm: Restrict v8M IDAU to TCGPhilippe Mathieu-Daudé2021-03-052-7/+8
| * | target/arm: Use TCF0 and TFSRE0 for unprivileged tag checksPeter Collingbourne2021-03-052-5/+10
| * | target/arm: Speed up aarch64 TBL/TBXRichard Henderson2021-03-054-84/+56Star
| * | target/arm: Set ID_PFR2.SSBS to 1 for "max" 32-bit CPURebecca Cran2021-03-051-0/+4
| * | target/arm: Enable FEAT_SSBS for "max" AARCH64 CPURebecca Cran2021-03-051-0/+5
| * | target/arm: Add support for FEAT_SSBS, Speculative Store Bypass SafeRebecca Cran2021-03-054-1/+69
* | | Merge remote-tracking branch 'remotes/cohuck-gitlab/tags/s390x-20210305' into...Peter Maydell2021-03-054-3/+20
|\ \ \ | |/ / |/| |
| * | target/s390x/kvm: Simplify debug codePhilippe Mathieu-Daudé2021-03-041-2/+1Star
| * | css: SCHIB measurement block origin must be alignedPierre Morel2021-03-041-0/+6
| * | target/s390x/arch_dump: Fix warning for the name field in the PT_NOTE sectionThomas Huth2021-03-041-1/+3
| * | s390x/cpu_model: disallow unpack for --only-migratableChristian Borntraeger2021-03-041-0/+10
| |/
* | target-riscv: support QMP dump-guest-memoryYifei Jiang2021-03-045-0/+210
* | target/riscv: Declare csr_ops[] with a known sizeBin Meng2021-03-041-1/+1
|/
* Merge remote-tracking branch 'remotes/bonzini-gitlab/tags/for-upstream' into ...Peter Maydell2021-03-023-3/+6
|\
| * tcg/i386: rdpmc: fix the the condtionsZheng Zhan Liang2021-02-251-1/+2
| * target/i386: Add bus lock debug exception supportChenyi Qiang2021-02-252-1/+3
| * target/i386: update to show preferred boolean syntax for -cpuDaniel P. Berrangé2021-02-251-1/+1
* | target/cris: Plug leakage of TCG temporariesStefan Sandstrom2021-02-222-59/+135
* | target/cris: Let cris_mmu_translate() use MMUAccessType access_typePhilippe Mathieu-Daudé2021-02-222-13/+13
* | target/cris: Use MMUAccessType enum type when possiblePhilippe Mathieu-Daudé2021-02-222-9/+8Star
|/
* Merge remote-tracking branch 'remotes/philmd-gitlab/tags/mips-20210221' into ...Peter Maydell2021-02-217-122/+123
|\
| * target/mips: Use GPR move functions in gen_HILO1_tx79()Philippe Mathieu-Daudé2021-02-211-17/+4Star
| * target/mips: Introduce gen_load_gpr_hi() / gen_store_gpr_hi() helpersPhilippe Mathieu-Daudé2021-02-212-0/+22
| * target/mips: Rename 128-bit upper halve GPR registersPhilippe Mathieu-Daudé2021-02-211-1/+3
| * target/mips: Promote 128-bit multimedia registers as global onesPhilippe Mathieu-Daudé2021-02-213-27/+34
| * target/mips: Make cpu_HI/LO registers publicPhilippe Mathieu-Daudé2021-02-212-1/+2
| * target/mips: Include missing "tcg/tcg.h" headerPhilippe Mathieu-Daudé2021-02-211-0/+1
| * target/mips: Remove unused 'rw' argument from page_table_walk_refill()Philippe Mathieu-Daudé2021-02-211-3/+3
| * target/mips: Let CPUMIPSTLBContext::map_address() take MMUAccessTypePhilippe Mathieu-Daudé2021-02-212-10/+10
| * target/mips: Let get_seg*_physical_address() take MMUAccessType argPhilippe Mathieu-Daudé2021-02-211-5/+6
| * target/mips: Let get_physical_address() take MMUAccessType argumentPhilippe Mathieu-Daudé2021-02-211-10/+10
| * target/mips: Let raise_mmu_exception() take MMUAccessType argumentPhilippe Mathieu-Daudé2021-02-211-5/+5
| * target/mips: Let cpu_mips_translate_address() take MMUAccessType argPhilippe Mathieu-Daudé2021-02-212-4/+4
| * target/mips: Let do_translate_address() take MMUAccessType argumentPhilippe Mathieu-Daudé2021-02-211-3/+4
| * target/mips: Replace magic value by MMU_DATA_LOAD definitionPhilippe Mathieu-Daudé2021-02-212-2/+2
| * target/mips: Remove unused MMU definitionsPhilippe Mathieu-Daudé2021-02-211-16/+0Star
| * target/mips: Remove access_type argument from get_physical_address()Philippe Mathieu-Daudé2021-02-211-13/+9Star
| * target/mips: Remove access_type arg from get_segctl_physical_address()Philippe Mathieu-Daudé2021-02-211-10/+10
| * target/mips: Remove access_type argument from get_seg_physical_addressPhilippe Mathieu-Daudé2021-02-211-3/+3
generated by cgit v1.2.3-55-g7522 (git 2.39.0) at 2024-12-18 11:59:07 +0100