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path: root/target/riscv/cpu.h
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* target/riscv: rvb: add b-ext version cpu optionFrank Chang2021-06-081-0/+3
* target/riscv: rvb: support and turn on B-extension from command lineKito Cheng2021-06-081-0/+1
* target/riscv: rvb: count leading/trailing zerosKito Cheng2021-06-081-0/+1
* target/riscv: Remove unnecessary riscv_*_names[] declarationBin Meng2021-06-081-2/+0Star
* target/riscv: Do not include 'pmp.h' in user emulationPhilippe Mathieu-Daudé2021-06-081-0/+2
* target/riscv: Remove the hardcoded RVXLEN macroAlistair Francis2021-05-111-6/+0Star
* target/riscv: Add a config option for ePMPHou Weiying2021-05-111-0/+1
* target/riscv: Add ePMP CSR access functionsHou Weiying2021-05-111-0/+1
* target/riscv: Add the ePMP featureAlistair Francis2021-05-111-0/+1
* target/riscv: Use RISCVException enum for CSR accessAlistair Francis2021-05-111-4/+7
* target/riscv: Use the RISCVException enum for CSR operationsAlistair Francis2021-05-111-6/+8
* target/riscv: Use the RISCVException enum for CSR predicatesAlistair Francis2021-05-111-1/+2
* target/riscv: Add Shakti C class CPUVijai Kumar K2021-05-111-0/+1
* target/riscv: Remove privilege v1.9 specific CSR related codeAtish Patra2021-05-111-3/+1Star
* target/riscv: Add proper two-stage lookup exception detectionGeorg Kotheimer2021-03-231-0/+4
* target-riscv: support QMP dump-guest-memoryYifei Jiang2021-03-041-0/+4
* target/riscv: Declare csr_ops[] with a known sizeBin Meng2021-03-041-1/+1
* target/riscv: Generate the GDB XML file for CSR registers dynamicallyBin Meng2021-01-161-0/+2
* target/riscv: Add CSR name in the CSR function tableBin Meng2021-01-161-0/+1
* target/riscv: Make csr_ops[CSR_TABLE_SIZE] externalBin Meng2021-01-161-0/+8
* target/riscv: Add a riscv_cpu_is_32bit() helper functionAlistair Francis2020-12-181-0/+2
* target/riscv: Add a TYPE_RISCV_CPU_BASE CPUAlistair Francis2020-12-181-0/+6
* target/riscv: Remove the hyp load and store functionsAlistair Francis2020-11-101-0/+12
* target/riscv: Remove the HS_TWO_STAGE flagAlistair Francis2020-11-101-2/+1Star
* target/riscv: Add a virtualised MMU ModeAlistair Francis2020-11-101-1/+3
* target/riscv: Merge m/vsstatus and m/vsstatush into one uint64_t unitYifei Jiang2020-11-031-13/+11Star
* target/riscv: raise exception to HS-mode at get_physical_addressYifei Jiang2020-10-221-3/+7
* qom: Remove module_obj_name parameter from OBJECT_DECLARE* macrosEduardo Habkost2020-09-181-1/+1
* Merge remote-tracking branch 'remotes/alistair/tags/pull-riscv-to-apply-20200...Peter Maydell2020-09-131-2/+6
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| * hw/riscv: clint: Avoid using hard-coded timebase frequencyBin Meng2020-09-101-2/+4
| * target/riscv: cpu: Add a new 'resetvec' propertyBin Meng2020-09-101-0/+1
| * target/riscv: Fix bug in getting trap cause name for trace_riscv_trapYifei Jiang2020-09-101-0/+1
* | Use OBJECT_DECLARE_TYPE where possibleEduardo Habkost2020-09-091-4/+2Star
* | Use DECLARE_*CHECKER* macrosEduardo Habkost2020-09-091-6/+2Star
* | Move QOM typedefs and add missing includesEduardo Habkost2020-09-091-4/+7
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* target/riscv: Allow setting a two-stage lookup in the virt statusAlistair Francis2020-08-251-0/+2
* target/riscv: fix vill bit index in vtype registerFrank Chang2020-07-141-1/+1
* target/riscv: configure and turn on vector extension from command lineLIU Zhiwei2020-07-021-1/+3
* target/riscv: add vector configure instructionLIU Zhiwei2020-07-021-9/+54
* target/riscv: implementation-defined constant parametersLIU Zhiwei2020-07-021-0/+5
* target/riscv: add vector extension field in CPURISCVStateLIU Zhiwei2020-07-021-0/+12
* target/riscv: Add the lowRISC Ibex CPUAlistair Francis2020-06-031-0/+1
* target/riscv: Drop support for ISA spec version 1.09.1Alistair Francis2020-06-031-1/+0Star
* target/riscv: Remove the deprecated CPUsAlistair Francis2020-06-031-7/+0Star
* target/riscv: Add a sifive-e34 cpu typeCorey Wharton2020-04-291-0/+1
* Merge remote-tracking branch 'remotes/ehabkost/tags/x86-and-machine-pull-requ...Peter Maydell2020-03-191-1/+1
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| * cpu: Use DeviceClass reset instead of a special CPUClass resetPeter Maydell2020-03-181-1/+1
* | gdbstub: extend GByteArray to read register helpersAlex Bennée2020-03-171-1/+1
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* target/riscv: Emulate TIME CSRs for privileged modeAnup Patel2020-02-271-0/+5
* target/riscv: Allow enabling the Hypervisor extensionAlistair Francis2020-02-271-0/+1
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