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path: root/target/riscv/cpu_bits.h
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* target-riscv: support QMP dump-guest-memoryYifei Jiang2021-03-041-0/+1
* riscv: Add semihosting supportKeith Packard2021-01-181-0/+1
* target/riscv: csr: Remove compile time XLEN checksAlistair Francis2020-12-181-3/+1Star
* target/riscv: Fix definition of MSTATUS_TW and MSTATUS_TSRAlex Richardson2020-12-181-2/+2
* target/riscv: Remove the HS_TWO_STAGE flagAlistair Francis2020-11-101-1/+0Star
* target/riscv: Merge m/vsstatus and m/vsstatush into one uint64_t unitYifei Jiang2020-11-031-15/+4Star
* target/riscv: Support the Virtual Instruction faultAlistair Francis2020-08-251-0/+6
* target/riscv: Support the v0.6 Hypervisor extension CRSsAlistair Francis2020-08-251-0/+3
* target/riscv: Update the CSRs to the v0.6 Hyp extensionAlistair Francis2020-08-251-6/+8
* target/riscv: Update the Hypervisor trap return/entryAlistair Francis2020-08-251-0/+1
* target/riscv: Convert MSTATUS MTL to GVAAlistair Francis2020-08-251-2/+3
* target/riscv: Allow generating hlv/hlvx/hsv instructionsAlistair Francis2020-08-251-0/+1
* target/riscv: Allow setting a two-stage lookup in the virt statusAlistair Francis2020-08-251-0/+1
* target/riscv: support vector extension csrLIU Zhiwei2020-07-021-0/+15
* target/riscv: Add the MSTATUS_MPV_ISSET helper macroAlistair Francis2020-02-271-0/+11
* target/riscv: Add support for the 32-bit MSTATUSH CSRAlistair Francis2020-02-271-0/+3
* target/riscv: Add virtual register swapping functionAlistair Francis2020-02-271-0/+7
* target/riscv: Add the force HS exception modeAlistair Francis2020-02-271-0/+6
* target/riscv: Add the virtulisation modeAlistair Francis2020-02-271-0/+3
* target/riscv: Rename the H irqs to VS irqsAlistair Francis2020-02-271-6/+6
* target/riscv: Add support for the new execption numbersAlistair Francis2020-02-271-16/+19
* target/riscv: Add the Hypervisor CSRs to CPUStateAlistair Francis2020-02-271-13/+21
* target/riscv: Update the Hypervisor CSRs to v0.4Alistair Francis2019-09-171-17/+18
* target/riscv: Add the mcountinhibit CSRAlistair Francis2019-06-251-0/+1
* Supply missing header guardsMarkus Armbruster2019-06-121-0/+5
* target/riscv: Add the HGATP register masksAlistair Francis2019-05-241-0/+11
* target/riscv: Add the HSTATUS register masksAlistair Francis2019-05-241-0/+18
* target/riscv: Add Hypervisor CSR macrosAlistair Francis2019-05-241-3/+6
* target/riscv: Add the MPV and MTL mstatus bitsAlistair Francis2019-05-241-3/+2Star
* target/riscv: Mark privilege level 2 as reservedAlistair Francis2019-05-241-1/+1
* RISC-V: Fixes to CSR_* register macros.Jim Wilson2019-03-191-2/+33
* RISC-V: Add misa runtime write supportMichael Clark2019-02-121-0/+11
* RISC-V: Update CSR and interrupt definitionsMichael Clark2018-10-171-318/+365
* RISC-V: Improve page table walker spec complianceMichael Clark2018-09-041-2/+0Star
* RISC-V CPU Core DefinitionMichael Clark2018-03-061-0/+411
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