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spice_video_codecs
Experimental fork of QEMU with video encoding patches
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path:
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target
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riscv
/
debug.c
Commit message (
Expand
)
Author
Age
Files
Lines
*
target/riscv: debug: Add initial support of type 6 trigger
Frank Chang
2022-09-27
1
-4
/
+170
*
target/riscv: debug: Check VU/VS modes for type 2 trigger
Frank Chang
2022-09-27
1
-0
/
+10
*
target/riscv: debug: Create common trigger actions function
Frank Chang
2022-09-27
1
-2
/
+57
*
target/riscv: debug: Introduce tinfo CSR
Frank Chang
2022-09-27
1
-3
/
+7
*
target/riscv: debug: Restrict the range of tselect value can be written
Frank Chang
2022-09-27
1
-6
/
+3
*
target/riscv: debug: Introduce tdata1, tdata2, and tdata3 CSRs
Frank Chang
2022-09-27
1
-65
/
+38
*
target/riscv: debug: Introduce build_tdata1() to build tdata1 register content
Frank Chang
2022-09-27
1
-5
/
+10
*
target/riscv: debug: Determine the trigger type from tdata1.type
Frank Chang
2022-09-27
1
-55
/
+133
*
target/riscv/debug.c: keep experimental rv128 support working
Frédéric Pétrot
2022-06-10
1
-0
/
+2
*
target/riscv: csr: Hook debug CSR read/write
Bin Meng
2022-04-22
1
-0
/
+27
*
target/riscv: debug: Implement debug related TCGCPUOps
Bin Meng
2022-04-22
1
-0
/
+75
*
target/riscv: Add initial support for the Sdtrig extension
Bin Meng
2022-04-22
1
-0
/
+339