Commit message (Expand) | Author | Age | Files | Lines | |
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* | gdbstub: extend GByteArray to read register helpers | Alex Bennée | 2020-03-17 | 1 | -10/+10 |
* | target/riscv: Add the Hypervisor CSRs to CPUState | Alistair Francis | 2020-02-27 | 1 | -5/+6 |
* | riscv: Separate FPU register size from core register size in gdbstub [v2] | Keith Packard | 2020-02-10 | 1 | -9/+11 |
* | target/riscv: Make the priv register writable by GDB | Jonathan Behrens | 2019-10-28 | 1 | -0/+9 |
* | target/riscv: Expose "priv" register for GDB for reads | Jonathan Behrens | 2019-10-28 | 1 | -0/+23 |
* | target/riscv: Tell gdbstub the correct number of CSRs | Jonathan Behrens | 2019-10-28 | 1 | -2/+2 |
* | gdbstub: riscv: fix the fflags registers | KONRAD Frederic | 2019-09-17 | 1 | -2/+4 |
* | Include qemu-common.h exactly where needed | Markus Armbruster | 2019-06-12 | 1 | -1/+0 |
* | RISC-V: Add hooks to use the gdb xml files. | Jim Wilson | 2019-03-19 | 1 | -11/+339 |
* | RISC-V: Implement modular CSR helper interface | Michael Clark | 2019-01-08 | 1 | -2/+8 |
* | RISC-V GDB Stub | Michael Clark | 2018-03-06 | 1 | -0/+62 |