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path: root/target/riscv/helper.h
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* target/riscv: add support for zhinx/zhinxminWeiwei Li2022-03-031-1/+1
* target/riscv: add support for zfinxWeiwei Li2022-03-031-1/+1
* target/riscv: Don't save pc when exception returnLIU Zhiwei2022-01-211-2/+2
* target/riscv: helper functions to wrap calls to 128-bit csr insnsFrédéric Pétrot2022-01-081-0/+3
* target/riscv: support for 128-bit M extensionFrédéric Pétrot2022-01-081-0/+6
* target/riscv: rvv-1.0: rename vmandnot.mm and vmornot.mm to vmandn.mm and vmo...Frank Chang2021-12-201-2/+2
* target/riscv: rvv-1.0: add vector unit-stride mask load/store insnsFrank Chang2021-12-201-0/+2
* target/riscv: rvv-1.0: floating-point reciprocal estimate instructionFrank Chang2021-12-201-0/+4
* target/riscv: rvv-1.0: floating-point reciprocal square-root estimate instruc...Frank Chang2021-12-201-0/+4
* target/riscv: rvv-1.0: implement vstart CSRFrank Chang2021-12-201-0/+5
* target/riscv: rvv-1.0: narrowing floating-point/integer type-convertFrank Chang2021-12-201-10/+12
* target/riscv: add "set round to odd" rounding mode helper functionFrank Chang2021-12-201-0/+1
* target/riscv: rvv-1.0: widening floating-point/integer type-convertFrank Chang2021-12-201-0/+2
* target/riscv: rvv-1.0: remove vmford.vv and vmford.vfFrank Chang2021-12-201-6/+0Star
* target/riscv: rvv-1.0: remove widening saturating scaled multiply-addFrank Chang2021-12-201-22/+0Star
* target/riscv: rvv-1.0: narrowing fixed-point clip instructionsFrank Chang2021-12-201-12/+12
* target/riscv: rvv-1.0: floating-point slide instructionsFrank Chang2021-12-201-0/+7
* target/riscv: rvv-1.0: narrowing integer right shift instructionsFrank Chang2021-12-201-12/+12
* target/riscv: rvv-1.0: single-width averaging add and subtract instructionsFrank Chang2021-12-201-0/+16
* target/riscv: rvv-1.0: integer extension instructionsFrank Chang2021-12-201-0/+14
* target/riscv: rvv-1.0: register gather instructionsFrank Chang2021-12-201-0/+4
* target/riscv: rvv-1.0: find-first-set mask bit instructionFrank Chang2021-12-201-1/+1
* target/riscv: rvv-1.0: count population in mask instructionFrank Chang2021-12-201-1/+1
* target/riscv: rvv-1.0: load/store whole register instructionsFrank Chang2021-12-201-0/+21
* target/riscv: rvv-1.0: fault-only-first unit stride loadFrank Chang2021-12-201-22/+4Star
* target/riscv: rvv-1.0: index load and store instructionsFrank Chang2021-12-201-35/+32Star
* target/riscv: rvv-1.0: stride load and store instructionsFrank Chang2021-12-201-105/+24Star
* target/riscv: rvv-1.0: remove amo operations instructionsFrank Chang2021-12-201-27/+0Star
* target/riscv: zfh: half-precision floating-point classifyKito Cheng2021-12-201-0/+1
* target/riscv: zfh: half-precision floating-point compareKito Cheng2021-12-201-0/+3
* target/riscv: zfh: half-precision convert and moveKito Cheng2021-12-201-0/+12
* target/riscv: zfh: half-precision computationalKito Cheng2021-12-201-0/+13
* target/riscv: Add rev8 instruction, removing grev/greviPhilipp Tomsich2021-10-071-2/+0Star
* target/riscv: Add orc.b instruction for Zbb, removing gorc/gorciPhilipp Tomsich2021-10-071-2/+0Star
* target/riscv: Add instructions of the Zbc-extensionPhilipp Tomsich2021-10-071-0/+2
* target/riscv: Reorg csr instructionsRichard Henderson2021-09-011-3/+3
* target/riscv: rvb: generalized or-combineFrank Chang2021-06-081-0/+2
* target/riscv: rvb: generalized reverseFrank Chang2021-06-081-0/+4
* target/riscv: Consolidate RV32/64 32-bit instructionsAlistair Francis2021-05-111-10/+8Star
* target/riscv: fpu_helper: Match function defs in HELPER macrosAlistair Francis2020-12-181-16/+8Star
* target/riscv: Split the Hypervisor execute load helpersAlistair Francis2020-11-101-1/+2
* target/riscv: Remove the hyp load and store functionsAlistair Francis2020-11-101-2/+0Star
* target/riscv: Support the Virtual Instruction faultAlistair Francis2020-08-251-0/+1
* target/riscv: Allow generating hlv/hlvx/hsv instructionsAlistair Francis2020-08-251-0/+3
* target/riscv: vector compress instructionLIU Zhiwei2020-07-021-0/+5
* target/riscv: vector register gather instructionLIU Zhiwei2020-07-021-0/+9
* target/riscv: vector slide instructionsLIU Zhiwei2020-07-021-0/+17
* target/riscv: vector element index instructionLIU Zhiwei2020-07-021-0/+5
* target/riscv: vector iota instructionLIU Zhiwei2020-07-021-0/+5
* target/riscv: set-X-first mask bitLIU Zhiwei2020-07-021-0/+4
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