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path: root/target/riscv/insn32.decode
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* target/riscv: rvb: add/shift with prefix zero-extendKito Cheng2021-06-081-0/+3
* target/riscv: rvb: address calculationKito Cheng2021-06-081-0/+6
* target/riscv: rvb: generalized or-combineFrank Chang2021-06-081-0/+4
* target/riscv: rvb: generalized reverseFrank Chang2021-06-081-0/+4
* target/riscv: rvb: rotate (left/right)Kito Cheng2021-06-081-0/+6
* target/riscv: rvb: shift onesKito Cheng2021-06-081-0/+8
* target/riscv: rvb: single-bit instructionsFrank Chang2021-06-081-0/+17
* target/riscv: rvb: sign-extend instructionsKito Cheng2021-06-081-0/+3
* target/riscv: rvb: min/max instructionsKito Cheng2021-06-081-0/+4
* target/riscv: rvb: pack two words into one registerKito Cheng2021-06-081-0/+6
* target/riscv: rvb: logic-with-negateKito Cheng2021-06-081-0/+3
* target/riscv: rvb: count bits setFrank Chang2021-06-081-0/+2
* target/riscv: rvb: count leading/trailing zerosKito Cheng2021-06-081-1/+10
* target/riscv: reformat @sh format encoding for B-extensionKito Cheng2021-06-081-5/+5
* target/riscv: Fix the RV64H decode commentAlistair Francis2021-05-111-1/+1
* target/riscv: Consolidate RV32/64 32-bit instructionsAlistair Francis2021-05-111-1/+66
* target/riscv: Allow generating hlv/hlvx/hsv instructionsAlistair Francis2020-08-251-0/+11
* target/riscv: vector compress instructionLIU Zhiwei2020-07-021-0/+1
* target/riscv: vector register gather instructionLIU Zhiwei2020-07-021-0/+3
* target/riscv: vector slide instructionsLIU Zhiwei2020-07-021-0/+6
* target/riscv: floating-point scalar move instructionsLIU Zhiwei2020-07-021-0/+3
* target/riscv: integer scalar move instructionLIU Zhiwei2020-07-021-0/+1
* target/riscv: integer extract instructionLIU Zhiwei2020-07-021-0/+1
* target/riscv: vector element index instructionLIU Zhiwei2020-07-021-0/+2
* target/riscv: vector iota instructionLIU Zhiwei2020-07-021-0/+1
* target/riscv: set-X-first mask bitLIU Zhiwei2020-07-021-0/+3
* target/riscv: vmfirst find-first-set mask bitLIU Zhiwei2020-07-021-0/+1
* target/riscv: vector mask population count vmpopcLIU Zhiwei2020-07-021-0/+1
* target/riscv: vector mask-register logical instructionsLIU Zhiwei2020-07-021-0/+8
* target/riscv: vector widening floating-point reduction instructionsLIU Zhiwei2020-07-021-0/+2
* target/riscv: vector single-width floating-point reduction instructionsLIU Zhiwei2020-07-021-0/+4
* target/riscv: vector wideing integer reduction instructionsLIU Zhiwei2020-07-021-0/+2
* target/riscv: vector single-width integer reduction instructionsLIU Zhiwei2020-07-021-0/+8
* target/riscv: narrowing floating-point/integer type-convert instructionsLIU Zhiwei2020-07-021-0/+5
* target/riscv: widening floating-point/integer type-convert instructionsLIU Zhiwei2020-07-021-0/+5
* target/riscv: vector floating-point/integer type-convert instructionsLIU Zhiwei2020-07-021-0/+4
* target/riscv: vector floating-point merge instructionsLIU Zhiwei2020-07-021-0/+2
* target/riscv: vector floating-point classify instructionsLIU Zhiwei2020-07-021-0/+1
* target/riscv: vector floating-point compare instructionsLIU Zhiwei2020-07-021-0/+12
* target/riscv: vector floating-point sign-injection instructionsLIU Zhiwei2020-07-021-0/+6
* target/riscv: vector floating-point min/max instructionsLIU Zhiwei2020-07-021-0/+4
* target/riscv: vector floating-point square-root instructionLIU Zhiwei2020-07-021-0/+3
* target/riscv: vector widening floating-point fused multiply-add instructionsLIU Zhiwei2020-07-021-0/+8
* target/riscv: vector single-width floating-point fused multiply-add instructionsLIU Zhiwei2020-07-021-0/+16
* target/riscv: vector widening floating-point multiplyLIU Zhiwei2020-07-021-0/+2
* target/riscv: vector single-width floating-point multiply/divide instructionsLIU Zhiwei2020-07-021-0/+5
* target/riscv: vector widening floating-point add/subtract instructionsLIU Zhiwei2020-07-021-0/+8
* target/riscv: vector single-width floating-point add/subtract instructionsLIU Zhiwei2020-07-021-0/+5
* target/riscv: vector narrowing fixed-point clip instructionsLIU Zhiwei2020-07-021-0/+6
* target/riscv: vector single-width scaling shift instructionsLIU Zhiwei2020-07-021-0/+6
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