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path: root/target/riscv/insn_trans/trans_rvb.c.inc
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* target/riscv: support for 128-bit arithmetic instructionsFrédéric Pétrot2022-01-081-10/+10
* target/riscv: support for 128-bit shift instructionsFrédéric Pétrot2022-01-081-11/+11
* target/riscv: separation of bitwise logic and arithmetic helpersFrédéric Pétrot2022-01-081-3/+3
* target/riscv: Use gen_shift*_per_ol for RVB, RVIRichard Henderson2021-10-221-40/+52
* target/riscv: Use gen_unary_per_ol for RVBRichard Henderson2021-10-221-17/+16Star
* target/riscv: Adjust trans_rev8_32 for riscv64Richard Henderson2021-10-221-1/+6
* target/riscv: Replace DisasContext.w with DisasContext.olRichard Henderson2021-10-211-4/+4
* target/riscv: Fix orc.b implementationPhilipp Tomsich2021-10-211-5/+8
* target/riscv: Add zext.h instructions to Zbb, removing pack/packu/packhPhilipp Tomsich2021-10-071-72/+14Star
* target/riscv: Add rev8 instruction, removing grev/greviPhilipp Tomsich2021-10-071-32/+8Star
* target/riscv: Add orc.b instruction for Zbb, removing gorc/gorciPhilipp Tomsich2021-10-071-22/+17Star
* target/riscv: Reassign instructions to the Zbb-extensionPhilipp Tomsich2021-10-071-22/+29
* target/riscv: Add instructions of the Zbc-extensionPhilipp Tomsich2021-10-071-1/+31
* target/riscv: Reassign instructions to the Zbs-extensionPhilipp Tomsich2021-10-071-10/+15
* target/riscv: Remove shift-one instructions (proposed Zbo in pre-0.93 draft-B)Philipp Tomsich2021-10-071-70/+0Star
* target/riscv: Remove the W-form instructions from ZbsPhilipp Tomsich2021-10-071-56/+0Star
* target/riscv: Reassign instructions to the Zba-extensionPhilipp Tomsich2021-10-071-5/+11
* target/riscv: clwz must ignore high bits (use shift-left & changed logic)Philipp Tomsich2021-10-071-3/+5
* target/riscv: fix clzw implementation to operate on arg1Philipp Tomsich2021-10-071-1/+1
* target/riscv: Introduce temporary in gen_add_uw()Philipp Tomsich2021-10-071-2/+4
* target/riscv: Use gen_shift_imm_fn for slli_uwRichard Henderson2021-09-011-13/+6Star
* target/riscv: Use DisasExtend in shift operationsRichard Henderson2021-09-011-70/+59Star
* target/riscv: Add DisasExtend to gen_unaryRichard Henderson2021-09-011-15/+9Star
* target/riscv: Move gen_* helpers for RVBRichard Henderson2021-09-011-0/+234
* target/riscv: Add DisasExtend to gen_arith*Richard Henderson2021-09-011-15/+15
* target/riscv: Add DisasContext to gen_get_gpr, gen_set_gprRichard Henderson2021-09-011-2/+2
* target/riscv: rvb: add/shift with prefix zero-extendKito Cheng2021-06-081-0/+26
* target/riscv: rvb: address calculationKito Cheng2021-06-081-0/+24
* target/riscv: rvb: generalized or-combineFrank Chang2021-06-081-0/+26
* target/riscv: rvb: generalized reverseFrank Chang2021-06-081-0/+31
* target/riscv: rvb: rotate (left/right)Kito Cheng2021-06-081-0/+39
* target/riscv: rvb: shift onesKito Cheng2021-06-081-0/+52
* target/riscv: rvb: single-bit instructionsFrank Chang2021-06-081-0/+97
* target/riscv: rvb: sign-extend instructionsKito Cheng2021-06-081-0/+12
* target/riscv: rvb: min/max instructionsKito Cheng2021-06-081-0/+24
* target/riscv: rvb: pack two words into one registerKito Cheng2021-06-081-0/+32
* target/riscv: rvb: logic-with-negateKito Cheng2021-06-081-0/+18
* target/riscv: rvb: count bits setFrank Chang2021-06-081-0/+13
* target/riscv: rvb: count leading/trailing zerosKito Cheng2021-06-081-0/+44
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