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path: root/target/riscv/insn_trans/trans_rvv.c.inc
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* target/riscv: rvv-1.0: Add Zve32f support for narrowing type-convert insnsFrank Chang2022-01-211-0/+3
* target/riscv: rvv-1.0: Add Zve32f support for widening type-convert insnsFrank Chang2022-01-211-0/+18
* target/riscv: rvv-1.0: Add Zve32f support for single-width fp reduction insnsFrank Chang2022-01-211-0/+1
* target/riscv: rvv-1.0: Add Zve32f support for scalar fp insnsFrank Chang2022-01-211-0/+21
* target/riscv: rvv-1.0: Add Zve32f support for configuration insnsFrank Chang2022-01-211-2/+2
* target/riscv: rvv-1.0: Add Zve64f support for narrowing type-convert insnsFrank Chang2022-01-211-3/+6
* target/riscv: rvv-1.0: Add Zve64f support for widening type-convert insnsFrank Chang2022-01-211-7/+25
* target/riscv: rvv-1.0: Add Zve64f support for single-width fp reduction insnsFrank Chang2022-01-211-1/+2
* target/riscv: rvv-1.0: Add Zve64f support for scalar fp insnsFrank Chang2022-01-211-10/+31
* target/riscv: rvv-1.0: Add Zve64f support for vsmul.vv and vsmul.vx insnsFrank Chang2022-01-211-2/+25
* target/riscv: rvv-1.0: Add Zve64f support for vmulh variant insnsFrank Chang2022-01-211-6/+33
* target/riscv: rvv-1.0: Add Zve64f support for load and store insnsFrank Chang2022-01-211-4/+15
* target/riscv: rvv-1.0: Add Zve64f support for configuration insnsFrank Chang2022-01-211-2/+4
* target/riscv: rvv-1.0: Call the correct RVF/RVD check function for narrowing ...Frank Chang2022-01-081-8/+24
* target/riscv: rvv-1.0: Call the correct RVF/RVD check function for widening f...Frank Chang2022-01-081-9/+25
* target/riscv: rvv-1.0: Call the correct RVF/RVD check function for widening f...Frank Chang2022-01-081-4/+8
* target/riscv: rvv-1.0: Add ELEN checks for widening and narrowing instructionsFrank Chang2021-12-201-6/+11
* target/riscv: rvv-1.0: update opivv_vadc_check() commentFrank Chang2021-12-201-1/+1
* target/riscv: rvv-1.0: rename vmandnot.mm and vmornot.mm to vmandn.mm and vmo...Frank Chang2021-12-201-2/+2
* target/riscv: rvv-1.0: add vector unit-stride mask load/store insnsFrank Chang2021-12-201-0/+40
* target/riscv: rvv-1.0: add vsetivli instructionFrank Chang2021-12-201-0/+27
* target/riscv: rvv-1.0: floating-point reciprocal estimate instructionFrank Chang2021-12-201-0/+1
* target/riscv: rvv-1.0: floating-point reciprocal square-root estimate instruc...Frank Chang2021-12-201-0/+1
* target/riscv: rvv-1.0: trigger illegal instruction exception if frm is not validFrank Chang2021-12-201-0/+22
* target/riscv: rvv-1.0: implement vstart CSRFrank Chang2021-12-201-27/+48
* target/riscv: rvv-1.0: relax RV_VLEN_MAX to 1024-bitsFrank Chang2021-12-201-2/+2
* target/riscv: rvv-1.0: narrowing floating-point/integer type-convertFrank Chang2021-12-201-9/+50
* target/riscv: rvv-1.0: widening floating-point/integer type-convertFrank Chang2021-12-201-8/+47
* target/riscv: rvv-1.0: floating-point/integer type-convert instructionsFrank Chang2021-12-201-32/+52
* target/riscv: introduce floating-point rounding mode enumFrank Chang2021-12-201-9/+9
* target/riscv: rvv-1.0: remove integer extract instructionFrank Chang2021-12-201-23/+0Star
* target/riscv: rvv-1.0: remove vmford.vv and vmford.vfFrank Chang2021-12-201-2/+0Star
* target/riscv: rvv-1.0: remove widening saturating scaled multiply-addFrank Chang2021-12-201-9/+0Star
* target/riscv: rvv-1.0: single-width scaling shift instructionsFrank Chang2021-12-201-2/+2
* target/riscv: rvv-1.0: widening floating-point reduction instructionsFrank Chang2021-12-201-1/+8
* target/riscv: rvv-1.0: single-width floating-point reductionFrank Chang2021-12-201-3/+9
* target/riscv: rvv-1.0: narrowing fixed-point clip instructionsFrank Chang2021-12-201-6/+6
* target/riscv: rvv-1.0: floating-point slide instructionsFrank Chang2021-12-201-0/+16
* target/riscv: rvv-1.0: mask-register logical instructionsFrank Chang2021-12-201-1/+2
* target/riscv: rvv-1.0: integer comparison instructionsFrank Chang2021-12-201-2/+2
* target/riscv: rvv-1.0: single-width saturating add and subtract instructionsFrank Chang2021-12-201-1/+1
* target/riscv: rvv-1.0: narrowing integer right shift instructionsFrank Chang2021-12-201-21/+21
* target/riscv: rvv-1.0: integer add-with-carry/subtract-with-borrowFrank Chang2021-12-201-1/+1
* target/riscv: rvv-1.0: single-width bit shift instructionsFrank Chang2021-12-201-3/+3
* target/riscv: rvv-1.0: single-width averaging add and subtract instructionsFrank Chang2021-12-201-1/+4
* target/riscv: rvv-1.0: integer extension instructionsFrank Chang2021-12-201-0/+80
* target/riscv: rvv-1.0: whole register move instructionsFrank Chang2021-12-201-0/+25
* target/riscv: rvv-1.0: floating-point scalar move instructionsFrank Chang2021-12-201-19/+19
* target/riscv: rvv-1.0: floating-point move instructionFrank Chang2021-12-201-2/+14
* target/riscv: rvv-1.0: integer scalar move instructionsFrank Chang2021-12-201-8/+35
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