summaryrefslogtreecommitdiffstats
path: root/target/riscv/insn_trans
Commit message (Expand)AuthorAgeFilesLines
* target/riscv: Split the Hypervisor execute load helpersAlistair Francis2020-11-101-14/+6Star
* target/riscv: Remove the hyp load and store functionsAlistair Francis2020-11-101-78/+45Star
* target/riscv: Support the Virtual Instruction faultAlistair Francis2020-08-251-1/+1
* target/riscv: Allow generating hlv/hlvx/hsv instructionsAlistair Francis2020-08-251-0/+340
* target/riscv: check before allocating TCG tempsLIU Zhiwei2020-08-222-8/+8
* target/riscv: Clean up fmv.w.xLIU Zhiwei2020-08-221-5/+1Star
* target/riscv: Check nanboxed inputs in trans_rvf.inc.cRichard Henderson2020-08-221-16/+55
* target/riscv: Generate nanboxed results from trans_rvf.inc.cRichard Henderson2020-08-221-0/+4
* target/riscv: Generalize gen_nanbox_fpr to gen_nanbox_sRichard Henderson2020-08-221-15/+1Star
* meson: rename included C source files to .c.incPaolo Bonzini2020-08-218-0/+0
* target/riscv: fix vector index load/store constraintsLIU Zhiwei2020-07-221-1/+9
* target/riscv: Quiet Coverity complains about vamo*LIU Zhiwei2020-07-221-0/+1
* target/riscv: fix return value of do_opivx_widen()Frank Chang2020-07-141-1/+1
* target/riscv: correct the gvec IR called in gen_vec_rsub16_i64()Frank Chang2020-07-141-1/+1
* target/riscv: fix rsub gvec tcg_assert_listed_vecop assertionFrank Chang2020-07-141-0/+5
* target/riscv: vector compress instructionLIU Zhiwei2020-07-021-0/+32
* target/riscv: vector register gather instructionLIU Zhiwei2020-07-021-0/+78
* target/riscv: vector slide instructionsLIU Zhiwei2020-07-021-0/+18
* target/riscv: floating-point scalar move instructionsLIU Zhiwei2020-07-021-0/+49
* target/riscv: integer scalar move instructionLIU Zhiwei2020-07-021-0/+60
* target/riscv: integer extract instructionLIU Zhiwei2020-07-021-0/+116
* target/riscv: vector element index instructionLIU Zhiwei2020-07-021-0/+25
* target/riscv: vector iota instructionLIU Zhiwei2020-07-021-0/+27
* target/riscv: set-X-first mask bitLIU Zhiwei2020-07-021-0/+28
* target/riscv: vmfirst find-first-set mask bitLIU Zhiwei2020-07-021-0/+32
* target/riscv: vector mask population count vmpopcLIU Zhiwei2020-07-021-0/+32
* target/riscv: vector mask-register logical instructionsLIU Zhiwei2020-07-021-0/+35
* target/riscv: vector widening floating-point reduction instructionsLIU Zhiwei2020-07-021-0/+3
* target/riscv: vector single-width floating-point reduction instructionsLIU Zhiwei2020-07-021-0/+5
* target/riscv: vector wideing integer reduction instructionsLIU Zhiwei2020-07-021-0/+4
* target/riscv: vector single-width integer reduction instructionsLIU Zhiwei2020-07-021-0/+18
* target/riscv: narrowing floating-point/integer type-convert instructionsLIU Zhiwei2020-07-021-0/+48
* target/riscv: widening floating-point/integer type-convert instructionsLIU Zhiwei2020-07-021-0/+48
* target/riscv: vector floating-point/integer type-convert instructionsLIU Zhiwei2020-07-021-0/+6
* target/riscv: vector floating-point merge instructionsLIU Zhiwei2020-07-021-0/+38
* target/riscv: vector floating-point classify instructionsLIU Zhiwei2020-07-021-0/+3
* target/riscv: vector floating-point compare instructionsLIU Zhiwei2020-07-021-0/+35
* target/riscv: vector floating-point sign-injection instructionsLIU Zhiwei2020-07-021-0/+8
* target/riscv: vector floating-point min/max instructionsLIU Zhiwei2020-07-021-0/+6
* target/riscv: vector floating-point square-root instructionLIU Zhiwei2020-07-021-0/+43
* target/riscv: vector widening floating-point fused multiply-add instructionsLIU Zhiwei2020-07-021-0/+10
* target/riscv: vector single-width floating-point fused multiply-add instructionsLIU Zhiwei2020-07-021-0/+18
* target/riscv: vector widening floating-point multiplyLIU Zhiwei2020-07-021-0/+4
* target/riscv: vector single-width floating-point multiply/divide instructionsLIU Zhiwei2020-07-021-0/+7
* target/riscv: vector widening floating-point add/subtract instructionsLIU Zhiwei2020-07-021-0/+149
* target/riscv: vector single-width floating-point add/subtract instructionsLIU Zhiwei2020-07-021-0/+118
* target/riscv: vector narrowing fixed-point clip instructionsLIU Zhiwei2020-07-021-0/+8
* target/riscv: vector single-width scaling shift instructionsLIU Zhiwei2020-07-021-0/+8
* target/riscv: vector widening saturating scaled multiply-addLIU Zhiwei2020-07-021-0/+9
* target/riscv: vector single-width fractional multiply with rounding and satur...LIU Zhiwei2020-07-021-0/+4
generated by cgit v1.2.3-55-g7522 (git 2.39.0) at 2024-12-18 12:11:12 +0100