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* target/riscv: zfh: half-precision convert and moveKito Cheng2021-12-201-0/+288
* target/riscv: zfh: half-precision computationalKito Cheng2021-12-201-0/+129
* target/riscv: zfh: half-precision load and storeKito Cheng2021-12-201-0/+65
* target/riscv: Support pointer masking for RISC-V for i/c/f/d/a types of instr...Alexey Baturo2021-10-284-0/+9
* target/riscv: Use gen_shift*_per_ol for RVB, RVIRichard Henderson2021-10-222-52/+66
* target/riscv: Use gen_unary_per_ol for RVBRichard Henderson2021-10-221-17/+16Star
* target/riscv: Adjust trans_rev8_32 for riscv64Richard Henderson2021-10-221-1/+6
* target/riscv: Use gen_arith_per_ol for RVMRichard Henderson2021-10-221-3/+23
* target/riscv: Replace DisasContext.w with DisasContext.olRichard Henderson2021-10-213-18/+18
* target/riscv: Properly check SEW in amo_opRichard Henderson2021-10-211-12/+14
* target/riscv: Use REQUIRE_64BIT in amo_check64Richard Henderson2021-10-211-1/+2
* target/riscv: Fix orc.b implementationPhilipp Tomsich2021-10-211-5/+8
* target/riscv: Pass the same value to oprsz and maxsz for vmv.v.vFrank Chang2021-10-211-1/+2
* target/riscv: Remove exit_tb and lookup_and_goto_ptrRichard Henderson2021-10-163-8/+6Star
* target/riscv: Remove dead code after exceptionRichard Henderson2021-10-161-5/+1Star
* target/riscv: Add zext.h instructions to Zbb, removing pack/packu/packhPhilipp Tomsich2021-10-071-72/+14Star
* target/riscv: Add rev8 instruction, removing grev/greviPhilipp Tomsich2021-10-071-32/+8Star
* target/riscv: Add orc.b instruction for Zbb, removing gorc/gorciPhilipp Tomsich2021-10-071-22/+17Star
* target/riscv: Reassign instructions to the Zbb-extensionPhilipp Tomsich2021-10-071-22/+29
* target/riscv: Add instructions of the Zbc-extensionPhilipp Tomsich2021-10-071-1/+31
* target/riscv: Reassign instructions to the Zbs-extensionPhilipp Tomsich2021-10-071-10/+15
* target/riscv: Remove shift-one instructions (proposed Zbo in pre-0.93 draft-B)Philipp Tomsich2021-10-071-70/+0Star
* target/riscv: Remove the W-form instructions from ZbsPhilipp Tomsich2021-10-071-56/+0Star
* target/riscv: Reassign instructions to the Zba-extensionPhilipp Tomsich2021-10-071-5/+11
* target/riscv: clwz must ignore high bits (use shift-left & changed logic)Philipp Tomsich2021-10-071-3/+5
* target/riscv: fix clzw implementation to operate on arg1Philipp Tomsich2021-10-071-1/+1
* target/riscv: Introduce temporary in gen_add_uw()Philipp Tomsich2021-10-071-2/+4
* target/riscv: Use {get,dest}_gpr for RVVRichard Henderson2021-09-011-53/+21Star
* target/riscv: Tidy trans_rvh.c.incRichard Henderson2021-09-011-210/+56Star
* target/riscv: Use {get,dest}_gpr for RVDRichard Henderson2021-09-011-65/+60Star
* target/riscv: Use {get,dest}_gpr for RVFRichard Henderson2021-09-011-76/+70Star
* target/riscv: Use gen_shift_imm_fn for slli_uwRichard Henderson2021-09-011-13/+6Star
* target/riscv: Use {get,dest}_gpr for RVARichard Henderson2021-09-011-28/+19Star
* target/riscv: Reorg csr instructionsRichard Henderson2021-09-011-52/+122
* target/riscv: Use {get, dest}_gpr for integer load/storeRichard Henderson2021-09-011-18/+20
* target/riscv: Use get_gpr in branchesRichard Henderson2021-09-011-15/+10Star
* target/riscv: Use extracts for sraiw and srliwRichard Henderson2021-09-011-2/+12
* target/riscv: Use DisasExtend in shift operationsRichard Henderson2021-09-012-140/+77Star
* target/riscv: Add DisasExtend to gen_unaryRichard Henderson2021-09-011-15/+9Star
* target/riscv: Move gen_* helpers for RVBRichard Henderson2021-09-011-0/+234
* target/riscv: Move gen_* helpers for RVMRichard Henderson2021-09-011-0/+127
* target/riscv: Use gen_arith for mulh and mulhuRichard Henderson2021-09-011-22/+18Star
* target/riscv: Remove gen_arith_div*Richard Henderson2021-09-011-8/+8
* target/riscv: Add DisasExtend to gen_arith*Richard Henderson2021-09-013-40/+45
* target/riscv: Add DisasContext to gen_get_gpr, gen_set_gprRichard Henderson2021-09-018-115/+115
* target/riscv: Use tcg_constant_*Richard Henderson2021-09-012-44/+24Star
* target/riscv: rvb: add/shift with prefix zero-extendKito Cheng2021-06-081-0/+26
* target/riscv: rvb: address calculationKito Cheng2021-06-081-0/+24
* target/riscv: rvb: generalized or-combineFrank Chang2021-06-081-0/+26
* target/riscv: rvb: generalized reverseFrank Chang2021-06-081-0/+31
generated by cgit v1.2.3-55-g7522 (git 2.39.0) at 2025-01-27 18:11:38 +0100