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path: root/target/riscv/machine.c
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* target/riscv: debug: Introduce tdata1, tdata2, and tdata3 CSRsFrank Chang2022-09-271-15/+5Star
* target/riscv: debug: Determine the trigger type from tdata1.typeFrank Chang2022-09-271-1/+1
* target/riscv: Set the CPU resetvec directlyAlistair Francis2022-09-261-3/+3
* target/riscv: Add sscofpmf extension supportAtish Patra2022-09-071-0/+1
* target/riscv: Add vstimecmp supportAtish Patra2022-09-071-0/+1
* target/riscv: Add stimecmp supportAtish Patra2022-09-071-0/+1
* hw/intc: Move mtimer/mtimecmp to aclintAtish Patra2022-09-071-3/+2Star
* target/riscv: Support mcycle/minstret write operationAtish Patra2022-07-031-2/+23
* target/riscv: Add support for hpmcounters/hpmeventsAtish Patra2022-07-031-0/+3
* target/riscv: Implement mcountinhibit CSRAtish Patra2022-07-031-0/+1
* target/riscv: machine: Add debug state descriptionBin Meng2022-04-221-0/+32
* target/riscv: Add *envcfg* CSRs supportAtish Patra2022-04-221-0/+23
* target/riscv: Implement AIA xiselect and xireg CSRsAnup Patel2022-02-161-0/+3
* target/riscv: Implement AIA hvictl and hviprioX CSRsAnup Patel2022-02-161-0/+2
* target/riscv: Implement AIA CSRs for 64 local interrupts on RV32Anup Patel2022-02-161-5/+5
* target/riscv: Implement AIA local interrupt prioritiesAnup Patel2022-02-161-0/+3
* target/riscv: Implement hgeie and hgeip CSRsAnup Patel2022-02-161-2/+4
* target/riscv: Split out the vill from vtypeLIU Zhiwei2022-01-211-2/+3
* target/riscv: Create current pm fields in envLIU Zhiwei2022-01-211-0/+1
* target/riscv: Create xl field in envLIU Zhiwei2022-01-211-0/+10
* target/riscv: Support virtual time context synchronizationYifei Jiang2022-01-211-0/+30
* target/riscv: adding high part of some csrsFrédéric Pétrot2022-01-081-0/+2
* target/riscv: array for the 64 upper bits of 128-bit registersFrédéric Pétrot2022-01-081-0/+20
* target/riscv: machine: Sort the .subsectionsBin Meng2021-11-171-46/+46
* target/riscv: Add J extension state descriptionAlexey Baturo2021-10-281-0/+27
* target/riscv: Split misa.mxl and misa.extRichard Henderson2021-10-211-4/+6
* target/riscv: Remove privilege v1.9 specific CSR related codeAtish Patra2021-05-111-5/+3Star
* target/riscv: Add V extension state descriptionYifei Jiang2020-11-031-0/+25
* target/riscv: Add H extension state descriptionYifei Jiang2020-11-031-0/+47
* target/riscv: Add PMP state descriptionYifei Jiang2020-11-031-0/+50
* target/riscv: Add basic vmstate description of CPUYifei Jiang2020-11-031-0/+74
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