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* target/riscv: Add stimecmp supportAtish Patra2022-09-071-1/+2
* meson: remove dead codePaolo Bonzini2022-09-011-2/+0Star
* target/riscv: Support mcycle/minstret write operationAtish Patra2022-07-031-1/+2
* target/riscv: rvk: add support for zknd/zkne extension in RV32Weiwei Li2022-04-291-1/+2
* target/riscv: Add initial support for the Sdtrig extensionBin Meng2022-04-221-0/+1
* target/riscv: Add XVentanaCondOps custom extensionPhilipp Tomsich2022-02-161-0/+1
* target/riscv: Support start kernel directly by KVMYifei Jiang2022-01-211-1/+1
* target/riscv: Add target/riscv/kvm.c to place the public kvm interfaceYifei Jiang2022-01-211-0/+1
* target/riscv: support for 128-bit M extensionFrédéric Pétrot2022-01-081-0/+1
* target/riscv: rvb: generalized reverseFrank Chang2021-06-081-0/+1
* target/riscv: Consolidate RV32/64 16-bit instructionsAlistair Francis2021-05-111-8/+3Star
* target/riscv: Consolidate RV32/64 32-bit instructionsAlistair Francis2021-05-111-1/+1
* target-riscv: support QMP dump-guest-memoryYifei Jiang2021-03-041-0/+1
* target/riscv: Add basic vmstate description of CPUYifei Jiang2020-11-031-1/+2
* meson: targetPaolo Bonzini2020-08-211-0/+34