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path: root/target/riscv/translate.c
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* target/riscv: rvv-1.0: add fractional LMULFrank Chang2021-12-201-2/+14
* target/riscv: rvv-1.0: remove MLEN calculationsFrank Chang2021-12-201-2/+0Star
* target/riscv: rvv-1.0: add translation-time vector context statusFrank Chang2021-12-201-0/+40
* target/riscv: zfh: implement zfhmin extensionFrank Chang2021-12-201-0/+2
* target/riscv: zfh: half-precision convert and moveKito Cheng2021-12-201-0/+10
* target/riscv: zfh: half-precision load and storeKito Cheng2021-12-201-0/+8
* target/riscv: Implement address masking functions required for RISC-V Pointer...Anatoly Parshintsev2021-10-281-2/+37
* target/riscv: Support pointer masking for RISC-V for i/c/f/d/a types of instr...Alexey Baturo2021-10-281-0/+8
* target/riscv: Compute mstatus.sd on demandRichard Henderson2021-10-221-3/+2Star
* target/riscv: Use gen_shift*_per_ol for RVB, RVIRichard Henderson2021-10-221-0/+31
* target/riscv: Use gen_unary_per_ol for RVBRichard Henderson2021-10-221-0/+16
* target/riscv: Use gen_arith_per_ol for RVMRichard Henderson2021-10-221-0/+16
* target/riscv: Replace DisasContext.w with DisasContext.olRichard Henderson2021-10-211-25/+44
* target/riscv: Replace is_32bit with get_xl/get_xlenRichard Henderson2021-10-211-14/+17
* target/riscv: Add MXL/SXL/UXL to TB_FLAGSRichard Henderson2021-10-211-1/+1
* target/riscv: Split misa.mxl and misa.extRichard Henderson2021-10-211-4/+6
* target/riscv: fix TB_FLAGS bits overlapping bug for rvv/rvhFrank Chang2021-10-211-1/+1
* target/riscv: Remove exit_tb and lookup_and_goto_ptrRichard Henderson2021-10-161-26/+1Star
* target/riscv: Set mstatus_hs.[SD|FS] bits if Clean and V=1 in mark_fs_dirty()Frank Chang2021-10-071-13/+17
* target/riscv: Add a REQUIRE_32BIT macroPhilipp Tomsich2021-10-071-0/+6
* accel/tcg: Add DisasContextBase argument to translator_ld*Ilya Leoshkevich2021-09-141-2/+3
* target/riscv: Use {get,dest}_gpr for RVVRichard Henderson2021-09-011-8/+5Star
* target/riscv: Use DisasExtend in shift operationsRichard Henderson2021-09-011-62/+48Star
* target/riscv: Add DisasExtend to gen_unaryRichard Henderson2021-09-011-8/+6Star
* target/riscv: Move gen_* helpers for RVBRichard Henderson2021-09-011-233/+0Star
* target/riscv: Move gen_* helpers for RVMRichard Henderson2021-09-011-127/+0Star
* target/riscv: Remove gen_arith_div*Richard Henderson2021-09-011-42/+0Star
* target/riscv: Add DisasExtend to gen_arith*Richard Henderson2021-09-011-50/+19Star
* target/riscv: Introduce DisasExtend and new helpersRichard Henderson2021-09-011-16/+81
* target/riscv: Add DisasContext to gen_get_gpr, gen_set_gprRichard Henderson2021-09-011-29/+29
* target/riscv: Clean up division helpersRichard Henderson2021-09-011-83/+91
* target/riscv: Use tcg_constant_*Richard Henderson2021-09-011-26/+10Star
* accel/tcg: Remove TranslatorOps.breakpoint_checkRichard Henderson2021-07-211-17/+0Star
* target/riscv: Use translator_use_goto_tbRichard Henderson2021-07-091-19/+1Star
* target/riscv: Use target_ulong for the DisasContext misaAlistair Francis2021-06-241-1/+1
* target/riscv: rvb: add/shift with prefix zero-extendKito Cheng2021-06-081-0/+6
* target/riscv: rvb: address calculationKito Cheng2021-06-081-0/+32
* target/riscv: rvb: generalized or-combineFrank Chang2021-06-081-0/+6
* target/riscv: rvb: generalized reverseFrank Chang2021-06-081-0/+28
* target/riscv: rvb: rotate (left/right)Kito Cheng2021-06-081-0/+36
* target/riscv: rvb: shift onesKito Cheng2021-06-081-0/+14
* target/riscv: rvb: single-bit instructionsFrank Chang2021-06-081-0/+61
* target/riscv: add gen_shifti() and gen_shiftiw() helper functionsFrank Chang2021-06-081-0/+39
* target/riscv: rvb: pack two words into one registerKito Cheng2021-06-081-0/+40
* target/riscv: rvb: count bits setFrank Chang2021-06-081-0/+6
* target/riscv: rvb: count leading/trailing zerosKito Cheng2021-06-081-0/+38
* target/riscv: Consolidate RV32/64 32-bit instructionsAlistair Francis2021-05-111-3/+6
* target/riscv: Remove an unused CASE_OP_32_64 macroAlistair Francis2021-05-111-6/+0Star
* target/riscv: Remove the hardcoded MSTATUS_SD macroAlistair Francis2021-05-111-2/+17
* target/riscv: Remove privilege v1.9 specific CSR related codeAtish Patra2021-05-111-2/+2
generated by cgit v1.2.3-55-g7522 (git 2.39.0) at 2025-01-27 17:49:11 +0100