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path: root/target/riscv/translate.c
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* target/riscv: Split pm_enabled into mask and baseLIU Zhiwei2022-01-211-4/+8
* target/riscv: Calculate address according to XLENLIU Zhiwei2022-01-211-13/+12Star
* target/riscv: Alloc tcg global for cur_pm[mask|base]LIU Zhiwei2022-01-211-24/+8Star
* target/riscv: Sign extend pc for different XLENLIU Zhiwei2022-01-211-4/+21
* target/riscv: Sign extend link reg for jal and jalrLIU Zhiwei2022-01-211-3/+1Star
* target/riscv: rvv-1.0: Add Zve32f extension into RISC-VFrank Chang2022-01-211-0/+2
* target/riscv: rvv-1.0: Add Zve64f extension into RISC-VFrank Chang2022-01-211-0/+2
* target/riscv: Implement the stval/mtval illegal instructionAlistair Francis2022-01-081-0/+3
* target/riscv: Set the opcode in DisasContextAlistair Francis2022-01-081-0/+2
* target/riscv: support for 128-bit arithmetic instructionsFrédéric Pétrot2022-01-081-12/+51
* target/riscv: support for 128-bit shift instructionsFrédéric Pétrot2022-01-081-15/+43
* target/riscv: support for 128-bit U-type instructionsFrédéric Pétrot2022-01-081-0/+21
* target/riscv: support for 128-bit bitwise instructionsFrédéric Pétrot2022-01-081-2/+19
* target/riscv: accessors to registers upper part and 128-bit load/storeFrédéric Pétrot2022-01-081-0/+41
* target/riscv: array for the 64 upper bits of 128-bit registersFrédéric Pétrot2022-01-081-1/+4
* target/riscv: separation of bitwise logic and arithmetic helpersFrédéric Pétrot2022-01-081-0/+27
* target/riscv: additional macros to check instruction supportFrédéric Pétrot2022-01-081-4/+16
* target/riscv: rvv-1.0: Add ELEN checks for widening and narrowing instructionsFrank Chang2021-12-201-0/+2
* target/riscv: rvv-1.0: implement vstart CSRFrank Chang2021-12-201-1/+5
* target/riscv: add "set round to odd" rounding mode helper functionFrank Chang2021-12-201-0/+7
* target/riscv: rvv-1.0: add fractional LMULFrank Chang2021-12-201-2/+14
* target/riscv: rvv-1.0: remove MLEN calculationsFrank Chang2021-12-201-2/+0Star
* target/riscv: rvv-1.0: add translation-time vector context statusFrank Chang2021-12-201-0/+40
* target/riscv: zfh: implement zfhmin extensionFrank Chang2021-12-201-0/+2
* target/riscv: zfh: half-precision convert and moveKito Cheng2021-12-201-0/+10
* target/riscv: zfh: half-precision load and storeKito Cheng2021-12-201-0/+8
* target/riscv: Implement address masking functions required for RISC-V Pointer...Anatoly Parshintsev2021-10-281-2/+37
* target/riscv: Support pointer masking for RISC-V for i/c/f/d/a types of instr...Alexey Baturo2021-10-281-0/+8
* target/riscv: Compute mstatus.sd on demandRichard Henderson2021-10-221-3/+2Star
* target/riscv: Use gen_shift*_per_ol for RVB, RVIRichard Henderson2021-10-221-0/+31
* target/riscv: Use gen_unary_per_ol for RVBRichard Henderson2021-10-221-0/+16
* target/riscv: Use gen_arith_per_ol for RVMRichard Henderson2021-10-221-0/+16
* target/riscv: Replace DisasContext.w with DisasContext.olRichard Henderson2021-10-211-25/+44
* target/riscv: Replace is_32bit with get_xl/get_xlenRichard Henderson2021-10-211-14/+17
* target/riscv: Add MXL/SXL/UXL to TB_FLAGSRichard Henderson2021-10-211-1/+1
* target/riscv: Split misa.mxl and misa.extRichard Henderson2021-10-211-4/+6
* target/riscv: fix TB_FLAGS bits overlapping bug for rvv/rvhFrank Chang2021-10-211-1/+1
* target/riscv: Remove exit_tb and lookup_and_goto_ptrRichard Henderson2021-10-161-26/+1Star
* target/riscv: Set mstatus_hs.[SD|FS] bits if Clean and V=1 in mark_fs_dirty()Frank Chang2021-10-071-13/+17
* target/riscv: Add a REQUIRE_32BIT macroPhilipp Tomsich2021-10-071-0/+6
* accel/tcg: Add DisasContextBase argument to translator_ld*Ilya Leoshkevich2021-09-141-2/+3
* target/riscv: Use {get,dest}_gpr for RVVRichard Henderson2021-09-011-8/+5Star
* target/riscv: Use DisasExtend in shift operationsRichard Henderson2021-09-011-62/+48Star
* target/riscv: Add DisasExtend to gen_unaryRichard Henderson2021-09-011-8/+6Star
* target/riscv: Move gen_* helpers for RVBRichard Henderson2021-09-011-233/+0Star
* target/riscv: Move gen_* helpers for RVMRichard Henderson2021-09-011-127/+0Star
* target/riscv: Remove gen_arith_div*Richard Henderson2021-09-011-42/+0Star
* target/riscv: Add DisasExtend to gen_arith*Richard Henderson2021-09-011-50/+19Star
* target/riscv: Introduce DisasExtend and new helpersRichard Henderson2021-09-011-16/+81
* target/riscv: Add DisasContext to gen_get_gpr, gen_set_gprRichard Henderson2021-09-011-29/+29
generated by cgit v1.2.3-55-g7522 (git 2.39.0) at 2024-12-12 02:57:17 +0100