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* RISC-V: Add trailing '\n' to qemu_log() callsPhilippe Mathieu-Daudé2018-06-081-2/+4
* tcg: Pass tb and index to tcg_gen_exit_tb separatelyRichard Henderson2018-06-021-10/+10
* Make address_space_translate{, _cached}() take a MemTxAttrs argumentPeter Maydell2018-05-311-1/+1
* target/riscv: Honor CPU_DUMP_FPURichard Henderson2018-05-181-5/+7
* target/riscv: Remove floatX_maybe_silence_nan from conversionsRichard Henderson2018-05-181-4/+2Star
* Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20180510'...Peter Maydell2018-05-111-49/+17Star
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| * target/riscv: Use new atomic min/max expandersRichard Henderson2018-05-101-49/+17Star
* | target/riscv: convert to TranslatorOpsEmilio G. Cota2018-05-091-78/+80
* | target/riscv: convert to DisasContextBaseEmilio G. Cota2018-05-091-65/+64Star
* | target/riscv: convert to DisasJumpTypeEmilio G. Cota2018-05-091-44/+28Star
* | target/riscv: avoid integer overflow in next_page PC checkEmilio G. Cota2018-05-091-3/+3
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* RISC-V: No traps on writes to misa,minstret,mcycleMichael Clark2018-05-061-12/+13
* RISC-V: Make mtvec/stvec ignore vectored trapsMichael Clark2018-05-061-6/+8
* RISC-V: Add mcycle/minstret support for -icount autoMichael Clark2018-05-062-2/+28
* RISC-V: Use [ms]counteren CSRs when priv ISA >= v1.10Michael Clark2018-05-062-18/+50
* RISC-V: Allow S-mode mxr access when priv ISA >= v1.10Michael Clark2018-05-061-2/+5
* RISC-V: Clear mtval/stval on exceptions without infoMichael Clark2018-05-061-0/+8
* RISC-V: Hardwire satp to 0 for no-mmu caseMichael Clark2018-05-061-2/+5
* RISC-V: Update E and I extension orderMichael Clark2018-05-062-1/+2
* RISC-V: Remove erroneous comment from translate.cMichael Clark2018-05-061-1/+0Star
* RISC-V: Remove EM_RISCV ELF_MACHINE indirectionMichael Clark2018-05-061-1/+0Star
* RISC-V: Workaround for critical mstatus.FS bugMichael Clark2018-03-291-2/+15
* RISC-V: Convert cpu definition to future modelMichael Clark2018-03-281-54/+69
* Merge remote-tracking branch 'remotes/ehabkost/tags/machine-next-pull-request...Peter Maydell2018-03-201-0/+1
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| * cpu: add CPU_RESOLVING_TYPE macroIgor Mammedov2018-03-191-0/+1
* | RISC-V: Fix riscv_isa_string memory size bugMichael Clark2018-03-201-6/+6
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* RISC-V Build InfrastructureMichael Clark2018-03-061-0/+1
* RISC-V Linux User EmulationMichael Clark2018-03-061-0/+13
* RISC-V Physical Memory ProtectionMichael Clark2018-03-062-0/+444
* RISC-V TCG Code GenerationMichael Clark2018-03-062-0/+2342
* RISC-V GDB StubMichael Clark2018-03-061-0/+62
* RISC-V FPU SupportMichael Clark2018-03-061-0/+373
* RISC-V CPU HelpersMichael Clark2018-03-063-0/+1250
* RISC-V CPU Core DefinitionMichael Clark2018-03-063-0/+1139
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