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* target/riscv: Adjust csr write mask with XLENLIU Zhiwei2022-01-212-5/+10
* target/riscv: Relax debug check for pm writeLIU Zhiwei2022-01-211-0/+3
* target/riscv: Use gdb xml according to max mxlenLIU Zhiwei2022-01-212-24/+55
* target/riscv: Extend pc for runtime pc writeLIU Zhiwei2022-01-211-3/+19
* target/riscv: Ignore the pc bits above XLENLIU Zhiwei2022-01-211-1/+1
* target/riscv: Create xl field in envLIU Zhiwei2022-01-215-32/+46
* target/riscv: Sign extend pc for different XLENLIU Zhiwei2022-01-214-9/+27
* target/riscv: Sign extend link reg for jal and jalrLIU Zhiwei2022-01-212-6/+2Star
* target/riscv: Don't save pc when exception returnLIU Zhiwei2022-01-213-9/+6Star
* target/riscv: Adjust pmpcfg access with mxlLIU Zhiwei2022-01-212-8/+23
* target/riscv: rvv-1.0: Allow Zve32f extension to be turned onFrank Chang2022-01-211-0/+1
* target/riscv: rvv-1.0: Add Zve32f support for narrowing type-convert insnsFrank Chang2022-01-211-0/+3
* target/riscv: rvv-1.0: Add Zve32f support for widening type-convert insnsFrank Chang2022-01-211-0/+18
* target/riscv: rvv-1.0: Add Zve32f support for single-width fp reduction insnsFrank Chang2022-01-211-0/+1
* target/riscv: rvv-1.0: Add Zve32f support for scalar fp insnsFrank Chang2022-01-211-0/+21
* target/riscv: rvv-1.0: Add Zve32f support for configuration insnsFrank Chang2022-01-211-2/+2
* target/riscv: rvv-1.0: Add Zve32f extension into RISC-VFrank Chang2022-01-215-4/+7
* target/riscv: rvv-1.0: Allow Zve64f extension to be turned onFrank Chang2022-01-211-0/+1
* target/riscv: rvv-1.0: Add Zve64f support for narrowing type-convert insnsFrank Chang2022-01-211-3/+6
* target/riscv: rvv-1.0: Add Zve64f support for widening type-convert insnsFrank Chang2022-01-211-7/+25
* target/riscv: rvv-1.0: Add Zve64f support for single-width fp reduction insnsFrank Chang2022-01-211-1/+2
* target/riscv: rvv-1.0: Add Zve64f support for scalar fp insnsFrank Chang2022-01-211-10/+31
* target/riscv: rvv-1.0: Add Zve64f support for vsmul.vv and vsmul.vx insnsFrank Chang2022-01-211-2/+25
* target/riscv: rvv-1.0: Add Zve64f support for vmulh variant insnsFrank Chang2022-01-211-6/+33
* target/riscv: rvv-1.0: Add Zve64f support for load and store insnsFrank Chang2022-01-211-4/+15
* target/riscv: rvv-1.0: Add Zve64f support for configuration insnsFrank Chang2022-01-211-2/+4
* target/riscv: rvv-1.0: Add Zve64f extension into RISC-VFrank Chang2022-01-215-2/+16
* target/riscv: Support virtual time context synchronizationYifei Jiang2022-01-211-0/+30
* target/riscv: Implement virtual time adjusting with vm state changingYifei Jiang2022-01-211-0/+15
* target/riscv: Add kvm_riscv_get/put_regs_timerYifei Jiang2022-01-212-0/+79
* target/riscv: Add host cpu typeYifei Jiang2022-01-212-0/+16
* target/riscv: Handle KVM_EXIT_RISCV_SBI exitYifei Jiang2022-01-212-1/+113
* target/riscv: Support setting external interrupt by KVMYifei Jiang2022-01-214-1/+28
* target/riscv: Support start kernel directly by KVMYifei Jiang2022-01-216-1/+75
* target/riscv: Implement kvm_arch_put_registersYifei Jiang2022-01-211-1/+103
* target/riscv: Implement kvm_arch_get_registersYifei Jiang2022-01-211-1/+111
* target/riscv: Implement function kvm_arch_init_vcpuYifei Jiang2022-01-211-1/+33
* target/riscv: Add target/riscv/kvm.c to place the public kvm interfaceYifei Jiang2022-01-212-0/+134
* target/riscv: Implement the stval/mtval illegal instructionAlistair Francis2022-01-083-0/+8
* target/riscv: Fixup setting GVAAlistair Francis2022-01-081-15/+6Star
* target/riscv: Set the opcode in DisasContextAlistair Francis2022-01-081-0/+2
* target/riscv: actual functions to realize crs 128-bit insnsFrédéric Pétrot2022-01-083-30/+175
* target/riscv: modification of the trans_csrxx for 128-bit supportFrédéric Pétrot2022-01-081-43/+158
* target/riscv: helper functions to wrap calls to 128-bit csr insnsFrédéric Pétrot2022-01-084-0/+69
* target/riscv: adding high part of some csrsFrédéric Pétrot2022-01-082-0/+6
* target/riscv: support for 128-bit M extensionFrédéric Pétrot2022-01-086-13/+295
* target/riscv: support for 128-bit arithmetic instructionsFrédéric Pétrot2022-01-085-49/+222
* target/riscv: support for 128-bit shift instructionsFrédéric Pétrot2022-01-084-44/+270
* target/riscv: support for 128-bit U-type instructionsFrédéric Pétrot2022-01-082-4/+25
* target/riscv: support for 128-bit bitwise instructionsFrédéric Pétrot2022-01-081-2/+19
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