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* target/riscv: Implement the stval/mtval illegal instructionAlistair Francis2022-01-083-0/+8
* target/riscv: Fixup setting GVAAlistair Francis2022-01-081-15/+6Star
* target/riscv: Set the opcode in DisasContextAlistair Francis2022-01-081-0/+2
* target/riscv: actual functions to realize crs 128-bit insnsFrédéric Pétrot2022-01-083-30/+175
* target/riscv: modification of the trans_csrxx for 128-bit supportFrédéric Pétrot2022-01-081-43/+158
* target/riscv: helper functions to wrap calls to 128-bit csr insnsFrédéric Pétrot2022-01-084-0/+69
* target/riscv: adding high part of some csrsFrédéric Pétrot2022-01-082-0/+6
* target/riscv: support for 128-bit M extensionFrédéric Pétrot2022-01-086-13/+295
* target/riscv: support for 128-bit arithmetic instructionsFrédéric Pétrot2022-01-085-49/+222
* target/riscv: support for 128-bit shift instructionsFrédéric Pétrot2022-01-084-44/+270
* target/riscv: support for 128-bit U-type instructionsFrédéric Pétrot2022-01-082-4/+25
* target/riscv: support for 128-bit bitwise instructionsFrédéric Pétrot2022-01-081-2/+19
* target/riscv: accessors to registers upper part and 128-bit load/storeFrédéric Pétrot2022-01-084-10/+163
* target/riscv: moving some insns close to similar insnsFrédéric Pétrot2022-01-081-17/+17
* target/riscv: setup everything for rv64 to support rv128 executionFrédéric Pétrot2022-01-083-0/+26
* target/riscv: array for the 64 upper bits of 128-bit registersFrédéric Pétrot2022-01-084-1/+35
* target/riscv: separation of bitwise logic and arithmetic helpersFrédéric Pétrot2022-01-083-9/+36
* target/riscv: additional macros to check instruction supportFrédéric Pétrot2022-01-081-4/+16
* exec/memop: Adding signedness to quad definitionsFrédéric Pétrot2022-01-084-17/+17
* target/riscv: Fix position of 'experimental' commentPhilipp Tomsich2022-01-081-1/+2
* target/riscv: rvv-1.0: Call the correct RVF/RVD check function for narrowing ...Frank Chang2022-01-081-8/+24
* target/riscv: rvv-1.0: Call the correct RVF/RVD check function for widening f...Frank Chang2022-01-081-9/+25
* target/riscv: rvv-1.0: Call the correct RVF/RVD check function for widening f...Frank Chang2022-01-081-4/+8
* target/riscv: Enable the Hypervisor extension by defaultAlistair Francis2022-01-081-1/+1
* target/riscv: Mark the Hypervisor extension as non experimentalAlistair Francis2022-01-081-1/+1
* target/riscv/pmp: fix no pmp illegal intrsNikita Shubin2022-01-081-1/+2
* target/riscv: Enable bitmanip Zb[abcs] instructionsVineet Gupta2021-12-201-4/+4
* target/riscv: rvv-1.0: Add ELEN checks for widening and narrowing instructionsFrank Chang2021-12-202-6/+13
* target/riscv: rvv-1.0: update opivv_vadc_check() commentFrank Chang2021-12-201-1/+1
* target/riscv: rvv-1.0: rename vmandnot.mm and vmornot.mm to vmandn.mm and vmo...Frank Chang2021-12-204-8/+8
* target/riscv: rvv-1.0: add vector unit-stride mask load/store insnsFrank Chang2021-12-204-0/+67
* target/riscv: rvv-1.0: add evl parameter to vext_ldst_us()Frank Chang2021-12-201-18/+18
* target/riscv: rvv-1.0: add vsetivli instructionFrank Chang2021-12-202-0/+29
* target/riscv: rvv-1.0: rename r2_zimm to r2_zimm11Frank Chang2021-12-201-2/+2
* target/riscv: rvv-1.0: floating-point reciprocal estimate instructionFrank Chang2021-12-204-0/+197
* target/riscv: rvv-1.0: floating-point reciprocal square-root estimate instruc...Frank Chang2021-12-204-0/+189
* target/riscv: gdb: support vector registers for rv64 & rv32Hsiangkai Wang2021-12-203-0/+187
* target/riscv: rvv-1.0: trigger illegal instruction exception if frm is not validFrank Chang2021-12-201-0/+22
* target/riscv: rvv-1.0: implement vstart CSRFrank Chang2021-12-205-103/+199
* target/riscv: rvv-1.0: relax RV_VLEN_MAX to 1024-bitsFrank Chang2021-12-203-4/+4
* target/riscv: rvv-1.0: narrowing floating-point/integer type-convertFrank Chang2021-12-204-44/+97
* target/riscv: add "set round to odd" rounding mode helper functionFrank Chang2021-12-204-0/+14
* target/riscv: rvv-1.0: widening floating-point/integer type-convertFrank Chang2021-12-204-14/+63
* target/riscv: rvv-1.0: floating-point/integer type-convert instructionsFrank Chang2021-12-202-36/+59
* target/riscv: introduce floating-point rounding mode enumFrank Chang2021-12-203-15/+24
* target/riscv: rvv-1.0: floating-point min/max instructionsFrank Chang2021-12-201-12/+12
* target/riscv: rvv-1.0: remove integer extract instructionFrank Chang2021-12-202-24/+0Star
* target/riscv: rvv-1.0: remove vmford.vv and vmford.vfFrank Chang2021-12-204-17/+0Star
* target/riscv: rvv-1.0: remove widening saturating scaled multiply-addFrank Chang2021-12-204-243/+0Star
* target/riscv: rvv-1.0: single-width scaling shift instructionsFrank Chang2021-12-201-2/+2
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