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* Merge remote-tracking branch 'remotes/vivier2/tags/linux-user-for-5.1-pull-re...Peter Maydell2020-06-081-2/+4
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| * target/riscv/cpu: Restrict CPU migration to system-modePhilippe Mathieu-Daudé2020-06-051-2/+4
* | target/riscv: Add the lowRISC Ibex CPUAlistair Francis2020-06-032-0/+11
* | target/riscv: Don't set PMP feature in the cpu initAlistair Francis2020-06-031-5/+0Star
* | target/riscv: Disable the MMU correctlyAlistair Francis2020-06-031-2/+3
* | target/riscv: Don't overwrite the reset vectorAlistair Francis2020-06-031-1/+2
* | target/riscv: Drop support for ISA spec version 1.09.1Alistair Francis2020-06-037-200/+63Star
* | target/riscv: Remove the deprecated CPUsAlistair Francis2020-06-032-35/+0Star
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* target/riscv: Add a sifive-e34 cpu typeCorey Wharton2020-04-292-0/+11
* riscv: Fix Stage2 SV32 page table walkAnup Patel2020-04-291-6/+1Star
* riscv: AND stage-1 and stage-2 protection flagsAlistair Francis2020-04-291-3/+5
* riscv: Don't use stage-2 PTE lookup protection flagsAlistair Francis2020-04-291-1/+2
* Merge remote-tracking branch 'remotes/ehabkost/tags/x86-and-machine-pull-requ...Peter Maydell2020-03-192-4/+5
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| * cpu: Use DeviceClass reset instead of a special CPUClass resetPeter Maydell2020-03-182-4/+5
* | gdbstub: extend GByteArray to read register helpersAlex Bennée2020-03-172-11/+11
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* target/riscv: Fix VS mode interrupts forwarding.Rajnesh Kanwal2020-03-171-1/+8
* target/riscv: Correctly implement TSR trapAlistair Francis2020-03-171-1/+1
* RISC-V: Add a missing "," in riscv_excp_namesPalmer Dabbelt2020-03-051-2/+2
* target/riscv: Emulate TIME CSRs for privileged modeAnup Patel2020-02-273-4/+92
* target/riscv: Allow enabling the Hypervisor extensionAlistair Francis2020-02-272-0/+6
* target/riscv: Add the MSTATUS_MPV_ISSET helper macroAlistair Francis2020-02-274-4/+15
* target/riscv: Add support for the 32-bit MSTATUSH CSRAlistair Francis2020-02-276-0/+62
* target/riscv: Set htval and mtval2 on execptionsAlistair Francis2020-02-271-0/+10
* target/riscv: Raise the new execptions when 2nd stage translation failsAlistair Francis2020-02-271-6/+18
* target/riscv: Implement second stage MMUAlistair Francis2020-02-272-19/+175
* target/riscv: Allow specifying MMU stageAlistair Francis2020-02-271-9/+28
* target/riscv: Respect MPRV and SPRV for floating point opsAlistair Francis2020-02-271-1/+15
* target/riscv: Mark both sstatus and msstatus_hs as dirtyAlistair Francis2020-02-271-0/+13
* target/riscv: Disable guest FP support based on virtual statusAlistair Francis2020-02-271-0/+3
* target/riscv: Only set TB flags with FP status if enabledAlistair Francis2020-02-271-1/+4
* target/riscv: Remove the hret instructionAlistair Francis2020-02-272-6/+0Star
* target/riscv: Add hfence instructionsAlistair Francis2020-02-272-9/+54
* target/riscv: Add Hypervisor trap return supportAlistair Francis2020-02-271-10/+52
* target/riscv: Add hypvervisor trap supportAlistair Francis2020-02-271-10/+59
* target/riscv: Generate illegal instruction on WFI when V=1Alistair Francis2020-02-271-2/+3
* target/ricsv: Flush the TLB on virtulisation mode changesAlistair Francis2020-02-271-0/+5
* target/riscv: Add support for virtual interrupt settingAlistair Francis2020-02-271-5/+28
* target/riscv: Extend the SIP CSR to support virtulisationAlistair Francis2020-02-271-1/+12
* target/riscv: Extend the MIE CSR to support virtulisationAlistair Francis2020-02-271-4/+20
* target/riscv: Set VS bits in mideleg for Hyp extensionAlistair Francis2020-02-271-0/+3
* target/riscv: Add virtual register swapping functionAlistair Francis2020-02-273-0/+79
* target/riscv: Add Hypervisor machine CSRs accessesAlistair Francis2020-02-271-0/+27
* target/riscv: Add Hypervisor virtual CSRs accessesAlistair Francis2020-02-271-0/+116
* target/riscv: Add Hypervisor CSR access functionsAlistair Francis2020-02-271-2/+134
* target/riscv: Dump Hypervisor registers if enabledAlistair Francis2020-02-271-0/+33
* target/riscv: Print priv and virt in disas logAlistair Francis2020-02-271-0/+8
* target/riscv: Fix CSR perm checking for HS modeAlistair Francis2020-02-271-4/+14
* target/riscv: Add the force HS exception modeAlistair Francis2020-02-273-0/+26
* target/riscv: Add the virtulisation modeAlistair Francis2020-02-273-0/+25
* target/riscv: Rename the H irqs to VS irqsAlistair Francis2020-02-272-9/+9
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