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* RISC-V: Fixes to CSR_* register macros.Jim Wilson2019-03-191-2/+33
* target/riscv: Fix manually parsed 16 bit insnBastian Koppelmann2019-03-181-5/+25
* target/riscv: Remove decode_RV32_64G()Bastian Koppelmann2019-03-131-20/+1Star
* target/riscv: Remove gen_system()Bastian Koppelmann2019-03-131-34/+0Star
* target/riscv: Rename trans_arith to gen_arithBastian Koppelmann2019-03-133-18/+18
* target/riscv: Remove manual decoding of RV32/64M insnBastian Koppelmann2019-03-132-211/+164Star
* target/riscv: Remove shift and slt insn manual decodingBastian Koppelmann2019-03-132-71/+81
* target/riscv: make ADD/SUB/OR/XOR/AND insn use arg listsBastian Koppelmann2019-03-133-30/+34
* target/riscv: Move gen_arith_imm() decoding into trans_* functionsBastian Koppelmann2019-03-133-100/+108
* target/riscv: Remove manual decoding from gen_store()Bastian Koppelmann2019-03-132-11/+24
* target/riscv: Remove manual decoding from gen_load()Bastian Koppelmann2019-03-132-16/+25
* target/riscv: Remove manual decoding from gen_branch()Bastian Koppelmann2019-03-132-60/+33Star
* target/riscv: Remove gen_jalr()Bastian Koppelmann2019-03-132-39/+27Star
* target/riscv: Convert quadrant 2 of RVXC insns to decodetreeBastian Koppelmann2019-03-133-81/+134
* target/riscv: Convert quadrant 1 of RVXC insns to decodetreeBastian Koppelmann2019-03-133-117/+195
* target/riscv: Convert quadrant 0 of RVXC insns to decodetreeBastian Koppelmann2019-03-134-38/+154
* target/riscv: Convert RV priv insns to decodetreeBastian Koppelmann2019-03-133-56/+126
* target/riscv: Convert RV64D insns to decodetreeBastian Koppelmann2019-03-133-600/+91Star
* target/riscv: Convert RV32D insns to decodetreeBastian Koppelmann2019-03-133-0/+389
* target/riscv: Convert RV64F insns to decodetreeBastian Koppelmann2019-03-132-0/+66
* target/riscv: Convert RV32F insns to decodetreeBastian Koppelmann2019-03-133-0/+415
* target/riscv: Convert RV64A insns to decodetreeBastian Koppelmann2019-03-133-144/+71Star
* target/riscv: Convert RV32A insns to decodetreeBastian Koppelmann2019-03-133-0/+178
* target/riscv: Convert RVXM insns to decodetreeBastian Koppelmann2019-03-134-9/+137
* target/riscv: Convert RVXI csr insns to decodetreeBastian Koppelmann2019-03-133-42/+88
* target/riscv: Convert RVXI fence insns to decodetreeBastian Koppelmann2019-03-133-12/+21
* target/riscv: Convert RVXI arithmetic insns to decodetreeBastian Koppelmann2019-03-134-9/+206
* target/riscv: Convert RV64I load/store insns to decodetreeBastian Koppelmann2019-03-134-10/+50
* target/riscv: Convert RV32I load/store insns to decodetreeBastian Koppelmann2019-03-132-0/+58
* target/riscv: Convert RVXI branch insns to decodetreeBastian Koppelmann2019-03-133-11/+69
* target/riscv: Activate decodetree and implemnt LUI & AUIPCBastian Koppelmann2019-03-134-14/+92
* target/riscv: fix counter-enable checks in ctr()Xi Wang2019-02-121-3/+9
* RISC-V: Add misa runtime write supportMichael Clark2019-02-124-3/+68
* RISC-V: Add misa.MAFD checks to translateMichael Clark2019-02-121-0/+158
* RISC-V: Add misa to DisasContextMichael Clark2019-02-121-35/+40
* RISC-V: Add priv_ver to DisasContextAlistair Francis2019-02-121-2/+5
* RISC-V: Use riscv prefix consistently on cpu helpersMichael Clark2019-02-125-37/+36Star
* RISC-V: Implement mstatus.TSR/TW/TVMMichael Clark2019-02-122-8/+34
* RISC-V: Mark mstatus.fs dirtyRichard Henderson2019-02-122-13/+39
* RISC-V: Split out mstatus_fs from tb_flagsRichard Henderson2019-02-122-8/+8
* RISC-V: Implement existential predicates for CSRsMichael Clark2019-01-094-79/+105
* RISC-V: Implement atomic mip/sip CSR updatesMichael Clark2019-01-091-28/+28
* RISC-V: Implement modular CSR helper interfaceMichael Clark2019-01-086-606/+904
* Merge remote-tracking branch 'remotes/palmer/tags/riscv-for-master-3.2-part1'...Peter Maydell2019-01-033-11/+13
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| * riscv/cpu: use device_class_set_parent_realizeMao Zhongyi2018-12-201-2/+2
| * target/riscv/pmp.c: Fix pmp_decode_napot()Anup Patel2018-12-201-1/+1
| * RISC-V: Add hartid and \n to interrupt loggingMichael Clark2018-12-201-8/+10
* | Clean up includesMarkus Armbruster2018-12-201-1/+0Star
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* RISC-V: Respect fences for user-only emulatorsPalmer Dabbelt2018-11-141-2/+0Star
* target/riscv: Fix sfence.vm/a both available in any priv versionBastian Koppelmann2018-11-141-5/+13
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