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* target/riscv: cpu: Enable native debug featureBin Meng2022-04-221-1/+1
* target/riscv: machine: Add debug state descriptionBin Meng2022-04-221-0/+32
* target/riscv: csr: Hook debug CSR read/writeBin Meng2022-04-224-0/+90
* target/riscv: cpu: Add a config option for native debugBin Meng2022-04-222-1/+8
* target/riscv: debug: Implement debug related TCGCPUOpsBin Meng2022-04-223-0/+82
* hw/intc: Make RISC-V ACLINT mtime MMIO register writableFrank Chang2022-04-222-6/+6
* target/riscv/pmp: fix NAPOT range computation overflowNicolas Pitre2022-04-221-11/+3Star
* target/riscv: Use cpu_loop_exit_restore directly from mmu faultsRichard Henderson2022-04-221-3/+3
* target/riscv: fix start byte for vmv<nf>r.v when vstart != 0Weiwei Li2022-04-221-3/+5
* target/riscv: Add isa extenstion strings to the device treeAtish Patra2022-04-221-0/+60
* target/riscv: misa to ISA string conversion fixTsukasa OI2022-04-221-5/+5
* target/riscv: optimize helper for vmv<nr>r.vWeiwei Li2022-04-223-33/+18Star
* target/riscv: optimize condition assign for scale < 0Weiwei Li2022-04-221-5/+3Star
* target/riscv: Add initial support for the Sdtrig extensionBin Meng2022-04-224-0/+453
* target/riscv: Allow software access to MIP SEIPAlistair Francis2022-04-223-3/+23
* target/riscv: cpu: Fixup indentationAlistair Francis2022-04-221-10/+10
* target/riscv: Enable privileged spec version 1.12Atish Patra2022-04-222-3/+10
* target/riscv: Add *envcfg* CSRs supportAtish Patra2022-04-224-0/+174
* target/riscv: Add support for mconfigptrAtish Patra2022-04-222-0/+3
* target/riscv: Introduce privilege version field in the CSR ops.Atish Patra2022-04-222-35/+70
* target/riscv: Add the privileged spec version 1.12.0Atish Patra2022-04-221-0/+1
* target/riscv: Define simpler privileged spec version numberingAtish Patra2022-04-221-2/+5
* compiler.h: replace QEMU_NORETURN with G_NORETURNMarc-André Lureau2022-04-212-7/+7
* exec/translator: Pass the locked filepointer to disas_log hookRichard Henderson2022-04-201-4/+6
* Remove qemu-common.h include from most unitsMarc-André Lureau2022-04-061-1/+0Star
* Move CPU softfloat unions to cpu-float.hMarc-André Lureau2022-04-061-1/+1
* Replace config-time define HOST_WORDS_BIGENDIANMarc-André Lureau2022-04-062-3/+3
* target/riscv: rvv: Add missing early exit condition for whole register load/s...Yueh-Ting (eop) Chen2022-04-011-0/+5
* target/riscv: Avoid leaking "no translation" TLB entriesPalmer Dabbelt2022-04-011-6/+8
* target: Use ArchCPU as interface to target CPUPhilippe Mathieu-Daudé2022-03-061-1/+1
* target: Introduce and use OBJECT_DECLARE_CPU_TYPE() macroPhilippe Mathieu-Daudé2022-03-061-3/+1Star
* target: Use CPUArchState as interface to target-specific CPU statePhilippe Mathieu-Daudé2022-03-061-3/+2Star
* target: Include missing 'cpu.h'Philippe Mathieu-Daudé2022-03-061-0/+2
* misc: Add missing "sysemu/cpu-timers.h" includePhilippe Mathieu-Daudé2022-03-061-0/+1
* target/riscv: expose zfinx, zdinx, zhinx{min} propertiesWeiwei Li2022-03-031-0/+5
* target/riscv: add support for zhinx/zhinxminWeiwei Li2022-03-034-143/+296
* target/riscv: add support for zdinxWeiwei Li2022-03-032-78/+259
* target/riscv: add support for zfinxWeiwei Li2022-03-035-145/+369
* target/riscv: hardwire mstatus.FS to zero when enable zfinxWeiwei Li2022-03-033-6/+29
* target/riscv: add cfg properties for zfinx, zdinx and zhinx{min}Weiwei Li2022-03-032-0/+16
* target/riscv: fix inverted checks for ext_zb[abcs]Philipp Tomsich2022-03-031-4/+4
* target: Add missing "qemu/timer.h" includePhilippe Mathieu-Daudé2022-02-211-0/+1
* target/riscv: add support for svpbmt extensionWeiwei Li2022-02-163-1/+6
* target/riscv: add support for svinval extensionWeiwei Li2022-02-165-0/+85
* target/riscv: add support for svnapot extensionWeiwei Li2022-02-163-3/+18
* target/riscv: add PTE_A/PTE_D/PTE_U bits check for inner PTEWeiwei Li2022-02-161-0/+3
* target/riscv: Ignore reserved bits in PTE for RV64Guo Ren2022-02-163-1/+30
* target/riscv: Allow users to force enable AIA CSRs in HARTAnup Patel2022-02-162-0/+6
* target/riscv: Implement AIA IMSIC interface CSRsAnup Patel2022-02-161-0/+203
* target/riscv: Implement AIA xiselect and xireg CSRsAnup Patel2022-02-163-0/+187
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