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* target/riscv: add zicsr/zifencei to isa_stringHongren (Zenithal) Zheng2022-05-241-0/+2
* target/riscv: Set [m|s]tval for both illegal and virtual instruction trapsAnup Patel2022-05-244-5/+23
* target/riscv: Fix hstatus.GVA bit setting for traps taken from HS-modeAnup Patel2022-05-241-2/+1Star
* target/riscv: Fix csr number based privilege checkingAnup Patel2022-05-241-2/+6
* target/riscv: Fix typo of mimpid cpu optionFrank Chang2022-05-243-7/+7
* target/riscv: check 'I' and 'E' after checking 'G' in riscv_cpu_realizeWeiwei Li2022-05-241-12/+12
* target/riscv: Move/refactor ISA extension checksTsukasa OI2022-05-241-15/+16
* target/riscv: FP extension requirementsTsukasa OI2022-05-241-0/+25
* target/riscv: Change "G" expansionTsukasa OI2022-05-241-2/+5
* target/riscv: Disable "G" by defaultTsukasa OI2022-05-241-1/+1
* target/riscv: Fix coding style on "G" expansionTsukasa OI2022-05-241-2/+2
* target/riscv: Add short-isa-string optionTsukasa OI2022-05-242-1/+7
* target/riscv: Move Zhinx* extensions on ISA stringTsukasa OI2022-05-241-2/+2
* target/riscv: rvv: Fix early exit condition for whole register load/storeeopXD2022-05-241-27/+31
* target/riscv: Fix VS mode hypervisor CSR accessDylan Reid2022-05-241-5/+5
* Normalize header guard symbol definitionMarkus Armbruster2022-05-111-1/+1
* Clean up ill-advised or unusual header guardsMarkus Armbruster2022-05-111-2/+2
* target/riscv: add scalar crypto related extenstion strings to isa_stringWeiwei Li2022-04-291-0/+13
* target/riscv: Fix incorrect PTE merge in walk_pteRalf Ramsauer2022-04-291-4/+7
* target/riscv: rvk: expose zbk* and zk* propertiesWeiwei Li2022-04-291-0/+13
* target/riscv: rvk: add CSR support for ZkrWeiwei Li2022-04-294-3/+103
* target/riscv: rvk: add support for zksed/zksh extensionWeiwei Li2022-04-294-0/+95
* target/riscv: rvk: add support for sha512 related instructions for RV64 in zk...Weiwei Li2022-04-292-0/+58
* target/riscv: rvk: add support for sha512 related instructions for RV32 in zk...Weiwei Li2022-04-292-0/+106
* target/riscv: rvk: add support for sha256 related instructions in zknh extensionWeiwei Li2022-04-292-0/+60
* target/riscv: rvk: add support for zkne/zknd extension in RV64Weiwei Li2022-04-294-0/+243
* target/riscv: rvk: add support for zknd/zkne extension in RV32Weiwei Li2022-04-296-1/+196
* target/riscv: rvk: add support for zbkx extensionWeiwei Li2022-04-294-0/+51
* target/riscv: rvk: add support for zbkc extensionWeiwei Li2022-04-292-3/+4
* target/riscv: rvk: add support for zbkb extensionWeiwei Li2022-04-295-28/+174
* target/riscv: rvk: add cfg properties for zbk* and zk*Weiwei Li2022-04-292-0/+36
* target/riscv: Support configuarable marchid, mvendorid, mipid CSR valuesFrank Chang2022-04-293-4/+47
* target/riscv: cpu: Enable native debug featureBin Meng2022-04-221-1/+1
* target/riscv: machine: Add debug state descriptionBin Meng2022-04-221-0/+32
* target/riscv: csr: Hook debug CSR read/writeBin Meng2022-04-224-0/+90
* target/riscv: cpu: Add a config option for native debugBin Meng2022-04-222-1/+8
* target/riscv: debug: Implement debug related TCGCPUOpsBin Meng2022-04-223-0/+82
* hw/intc: Make RISC-V ACLINT mtime MMIO register writableFrank Chang2022-04-222-6/+6
* target/riscv/pmp: fix NAPOT range computation overflowNicolas Pitre2022-04-221-11/+3Star
* target/riscv: Use cpu_loop_exit_restore directly from mmu faultsRichard Henderson2022-04-221-3/+3
* target/riscv: fix start byte for vmv<nf>r.v when vstart != 0Weiwei Li2022-04-221-3/+5
* target/riscv: Add isa extenstion strings to the device treeAtish Patra2022-04-221-0/+60
* target/riscv: misa to ISA string conversion fixTsukasa OI2022-04-221-5/+5
* target/riscv: optimize helper for vmv<nr>r.vWeiwei Li2022-04-223-33/+18Star
* target/riscv: optimize condition assign for scale < 0Weiwei Li2022-04-221-5/+3Star
* target/riscv: Add initial support for the Sdtrig extensionBin Meng2022-04-224-0/+453
* target/riscv: Allow software access to MIP SEIPAlistair Francis2022-04-223-3/+23
* target/riscv: cpu: Fixup indentationAlistair Francis2022-04-221-10/+10
* target/riscv: Enable privileged spec version 1.12Atish Patra2022-04-222-3/+10
* target/riscv: Add *envcfg* CSRs supportAtish Patra2022-04-224-0/+174
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