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* target/riscv: Implementation of enhanced PMP (ePMP)Hou Weiying2021-05-111-8/+146
* target/riscv: Add ePMP CSR access functionsHou Weiying2021-05-115-0/+76
* target/riscv: Add the ePMP featureAlistair Francis2021-05-111-0/+1
* target/riscv: Define ePMP mseccfgHou Weiying2021-05-111-0/+3
* target/riscv: Fix the PMP is locked check when using TORAlistair Francis2021-05-111-10/+16
* target/riscv: Fixup saturate subtract functionLIU Zhiwei2021-05-111-4/+4
* riscv: don't look at SUM when accessing memory from a debugger contextJade Fink2021-05-111-8/+12
* target/riscv: Use RISCVException enum for CSR accessAlistair Francis2021-05-114-36/+38
* target/riscv: Use the RISCVException enum for CSR operationsAlistair Francis2021-05-112-261/+382
* target/riscv: Fix 32-bit HS mode access permissionsAlistair Francis2021-05-111-1/+5
* target/riscv: Use the RISCVException enum for CSR predicatesAlistair Francis2021-05-112-37/+46
* target/riscv: Convert the RISC-V exceptions to an enumAlistair Francis2021-05-113-24/+26
* target/riscv: Add Shakti C class CPUVijai Kumar K2021-05-112-0/+2
* target/riscv: Align the data type of reset vector addressDylan Jhong2021-05-111-1/+1
* target/riscv: Remove privilege v1.9 specific CSR related codeAtish Patra2021-05-117-72/+23Star
* hw: Do not include qemu/log.h if it is not necessaryThomas Huth2021-05-021-1/+0Star
* target/riscv: Prevent lost illegal instruction exceptionsGeorg Kotheimer2021-03-231-178/+1Star
* target/riscv: Add proper two-stage lookup exception detectionGeorg Kotheimer2021-03-233-13/+13
* target/riscv: Fix read and write accesses to vsip and vsieGeorg Kotheimer2021-03-231-34/+34
* target/riscv: Use background registers also for MSTATUS_MPVGeorg Kotheimer2021-03-231-1/+1
* target/riscv: Make VSTIP and VSEIP read-only in hipGeorg Kotheimer2021-03-231-3/+4
* target/riscv: Adjust privilege level for HLV(X)/HSV instructionsGeorg Kotheimer2021-03-231-11/+14
* target/riscv: flush TLB pages if PMP permission has been changedJim Shu2021-03-231-0/+4
* target/riscv: add log of PMP permission checkingJim Shu2021-03-231-0/+12
* target/riscv: propagate PMP permission to TLB pageJim Shu2021-03-233-43/+125
* target/riscv: fix vs() to return proper error codeFrank Chang2021-03-231-1/+1
* Merge remote-tracking branch 'remotes/vivier2/tags/trivial-branch-for-6.0-pul...Peter Maydell2021-03-111-1/+1
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| * Various spelling fixesMichael Tokarev2021-03-091-1/+1
* | semihosting: Move include/hw/semihosting/ -> include/semihosting/Philippe Mathieu-Daudé2021-03-101-1/+1
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* target-riscv: support QMP dump-guest-memoryYifei Jiang2021-03-045-0/+210
* target/riscv: Declare csr_ops[] with a known sizeBin Meng2021-03-041-1/+1
* cpu: tcg_ops: move to tcg-cpu-ops.h, keep a pointer in CPUClassClaudio Fontana2021-02-051-7/+16
* cpu: move do_unaligned_access to tcg_opsClaudio Fontana2021-02-051-1/+1
* cpu: move cc->transaction_failed to tcg_opsClaudio Fontana2021-02-052-2/+2
* cpu: move cc->do_interrupt to tcg_opsClaudio Fontana2021-02-051-1/+1
* cpu: Move tlb_fill to tcg_opsEduardo Habkost2021-02-051-1/+1
* cpu: Move cpu_exec_* to tcg_opsEduardo Habkost2021-02-051-1/+1
* cpu: Move synchronize_from_tb() to tcg_opsEduardo Habkost2021-02-051-1/+1
* target/riscv: remove CONFIG_TCG, as it is always TCGClaudio Fontana2021-02-051-2/+1Star
* cpu: Introduce TCGCpuOperations structEduardo Habkost2021-02-051-1/+1
* Merge remote-tracking branch 'remotes/stsquad/tags/pull-testing-and-misc-1801...Peter Maydell2021-01-184-1/+58
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| * riscv: Add semihosting supportKeith Packard2021-01-184-1/+58
* | target/riscv: Generate the GDB XML file for CSR registers dynamicallyBin Meng2021-01-163-264/+58Star
* | target/riscv: Add CSR name in the CSR function tableBin Meng2021-01-162-84/+249
* | target/riscv: Make csr_ops[CSR_TABLE_SIZE] externalBin Meng2021-01-162-9/+9
* | target/riscv/pmp: Raise exception if no PMP entry is configuredAtish Patra2021-01-163-2/+8
* | gdb: riscv: Add target descriptionSylvain Pelissier2021-01-161-0/+13
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* tcg: Make tb arg to synchronize_from_tb constRichard Henderson2021-01-071-1/+2
* target/riscv: cpu: Set XLEN independently from targetAlistair Francis2020-12-181-9/+16
* target/riscv: csr: Remove compile time XLEN checksAlistair Francis2020-12-182-88/+92
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