bwlp/qemu.git - Experimental fork of QEMU with video encoding patches

	Commit message (Expand)	Author	Age	Files	Lines
*	target/xtensa: add DFPU registers and opcodes	Max Filippov	2020-08-21	1	-0/+1
*	target/xtensa: add DFPU option	Max Filippov	2020-08-21	1	-0/+23
*	target/xtensa: implement NMI support	Max Filippov	2020-08-21	1	-1/+5
*	target/xtensa: fetch HW version from configuration overlay	Max Filippov	2020-05-17	1	-3/+5
*	target/xtensa: use MPU background map from core configuration	Max Filippov	2020-01-06	1	-1/+14
*	target/xtensa: implement exclusive access option	Max Filippov	2019-05-15	1	-2/+6
*	target/xtensa: implement DIWBUI.P opcode	Max Filippov	2019-05-14	1	-0/+1
*	target/xtensa: implement MPU option	Max Filippov	2019-05-11	1	-0/+29
*	target/xtensa: add parity/ECC option SRs	Max Filippov	2019-05-11	1	-0/+2
*	target/xtensa: define IDMA and gather/scatter IRQ types	Max Filippov	2019-05-11	1	-0/+3
*	target/xtensa: move xtensa_finalize_config to xtensa_core_class_init	Max Filippov	2019-02-19	1	-1/+0
*	target/xtensa: rework zero overhead loops implementation	Max Filippov	2019-01-12	1	-0/+1
*	target/xtensa: check zero overhead loop alignment	Max Filippov	2018-06-30	1	-0/+1
*	target/xtensa: use correct number of registers in gdbstub	Max Filippov	2018-03-13	1	-3/+8
*	target/xtensa: fix default sysrom/sysram addresses	Max Filippov	2018-01-11	1	-4/+4
*	target/xtensa: sim: instantiate local memories	Max Filippov	2017-02-23	1	-0/+160
*	target-xtensa: implement RER/WER instructions	Max Filippov	2017-01-17	1	-1/+6
*	target/xtensa: implement MEMCTL SR	Max Filippov	2017-01-15	1	-0/+15
*	target/xtensa: fix ICACHE/DCACHE options detection	Max Filippov	2017-01-15	1	-2/+2
*	target/xtensa: add static vectors selection	Max Filippov	2017-01-15	1	-1/+10
*	Move target-* CPU file into a target/ folder	Thomas Huth	2016-12-20	1	-0/+602