Commit message (Expand) | Author | Age | Files | Lines | |
---|---|---|---|---|---|
* | target-xtensa: implement RER/WER instructions | Max Filippov | 2017-01-17 | 1 | -1/+6 |
* | target/xtensa: implement MEMCTL SR | Max Filippov | 2017-01-15 | 1 | -0/+15 |
* | target/xtensa: fix ICACHE/DCACHE options detection | Max Filippov | 2017-01-15 | 1 | -2/+2 |
* | target/xtensa: add static vectors selection | Max Filippov | 2017-01-15 | 1 | -1/+10 |
* | Move target-* CPU file into a target/ folder | Thomas Huth | 2016-12-20 | 1 | -0/+602 |