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path: root/target/xtensa/translate.c
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* tcg: Search includes from the project root source directoryPhilippe Mathieu-Daudé2020-01-161-1/+1
* target/xtensa: fix ps.ring use in MPU configsMax Filippov2020-01-061-1/+2
* target/xtensa: fetch code with translator_ldEmilio G. Cota2019-10-281-2/+2
* icount: remove unnecessary gen_io_end callsPavel Dovgalyuk2019-08-201-15/+0Star
* Clean up inclusion of sysemu/sysemu.hMarkus Armbruster2019-08-161-1/+0Star
* semihosting: move semihosting configuration into its own directoryAlex Bennée2019-05-281-1/+1
* Merge remote-tracking branch 'remotes/xtensa/tags/20190520-xtensa' into stagingPeter Maydell2019-05-211-1005/+1942
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| * target/xtensa: implement exclusive access optionMax Filippov2019-05-151-0/+100
| * target/xtensa: implement block prefetch option opcodesMax Filippov2019-05-151-0/+42
| * target/xtensa: implement DIWBUI.P opcodeMax Filippov2019-05-141-0/+10
| * target/xtensa: implement MPU optionMax Filippov2019-05-111-0/+146
| * target/xtensa: add parity/ECC option SRsMax Filippov2019-05-111-0/+162
| * target/xtensa: get rid of centralized SR propertiesMax Filippov2019-05-111-1005/+1482
* | target/xtensa: Use tcg_gen_abs_i32Richard Henderson2019-05-141-8/+1Star
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* tcg: Hoist max_insns computation to tb_gen_codeRichard Henderson2019-04-241-2/+2
* qom/cpu: Simplify how CPUClass:cpu_dump_state() printsMarkus Armbruster2019-04-181-19/+21
* target/xtensa: fix break_dependency for repeated resourcesMax Filippov2019-03-221-1/+0Star
* target/xtensa: implement PREFCTL SRMax Filippov2019-02-281-0/+16
* target/xtensa: prioritize load/store in FLIX bundlesMax Filippov2019-02-281-5/+32
* target/xtensa: break circular register dependenciesMax Filippov2019-02-281-4/+123
* target/xtensa: reorganize access to boolean registersMax Filippov2019-02-281-8/+42
* target/xtensa: reorganize access to MAC16 registersMax Filippov2019-02-281-94/+92Star
* target/xtensa: reorganize register handling in translatorsMax Filippov2019-02-281-341/+359
* target/xtensa: only rotate window in the retw helperMax Filippov2019-02-281-2/+7
* target/xtensa: move WINDOW_BASE SR update to postprocessingMax Filippov2019-02-281-8/+22
* target/xtensa: add generic instruction post-processingMax Filippov2019-02-281-8/+25
* target/xtensa: sort FLIX instruction opcodesMax Filippov2019-02-281-8/+219
* target/xtensa: implement wide branches and loopsMax Filippov2019-02-191-27/+102
* target/xtensa: allow multiple names for single opcodeMax Filippov2019-02-191-56/+44Star
* target/xtensa: don't require opcode table sortingMax Filippov2019-02-191-14/+0Star
* target/xtensa: get rid of gen_callw[i]Max Filippov2019-02-111-21/+14Star
* target/xtensa: don't specify windowed registers manuallyMax Filippov2019-02-111-483/+10Star
* target/xtensa: fix access to the INTERRUPT SRMax Filippov2019-01-241-12/+2Star
* target/xtensa: rework zero overhead loops implementationMax Filippov2019-01-121-37/+16Star
* target/xtensa: extract gen_check_interrupts callMax Filippov2018-10-011-25/+53
* target/xtensa: make rsr/wsr helpers return voidMax Filippov2018-10-011-66/+36Star
* target/xtensa: extract unconditional TB termination via slot 0Max Filippov2018-10-011-47/+36Star
* target/xtensa: always end TB on CCOUNT access/CCOMPARE writeMax Filippov2018-10-011-8/+5Star
* target/xtensa: change SR number checks to assertionsMax Filippov2018-10-011-36/+29Star
* target/xtensa: extract unconditional TB terminationMax Filippov2018-10-011-39/+28Star
* target/xtensa: extract test for division by zeroMax Filippov2018-10-011-22/+31
* target/xtensa: extract test for cpdisabled exceptionMax Filippov2018-10-011-108/+122
* target/xtensa: extract test for alloca exceptionMax Filippov2018-10-011-3/+8
* target/xtensa: extract test for window underflow exceptionMax Filippov2018-10-011-0/+9
* target/xtensa: extract test for window overflow exceptionMax Filippov2018-10-011-582/+880
* target/xtensa: extract test for debug exceptionMax Filippov2018-10-011-10/+13
* target/xtensa: extract test for syscall instructionMax Filippov2018-10-011-7/+6Star
* target/xtensa: extract test for privileged instructionMax Filippov2018-10-011-93/+294
* target/xtensa: extract test for an illegal instructionMax Filippov2018-10-011-35/+332
* target/xtensa: fix s32c1i TCGMemOp flagsMax Filippov2018-09-171-1/+1
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