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path: root/target/xtensa/translate.c
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* target/xtensa: Use translator_use_goto_tbRichard Henderson2021-07-091-5/+1Star
* tcg: Avoid including 'trace-tcg.h' in target translate.cPhilippe Mathieu-Daudé2021-07-091-1/+0Star
* target/xtensa: clean up unaligned accessMax Filippov2021-05-201-59/+61
* target/xtensa: fix access ring in l32exMax Filippov2021-05-201-1/+1
* target/xtensa: don't generate extra EXCP_DEBUG on exceptionMax Filippov2021-05-201-6/+0Star
* target/xtensa: Make sure that tb->size != 0Ilya Leoshkevich2021-05-201-0/+3
* semihosting: Move include/hw/semihosting/ -> include/semihosting/Philippe Mathieu-Daudé2021-03-101-1/+1
* target/xtensa: implement FPU division and square rootMax Filippov2020-08-211-0/+104
* target/xtensa: add DFPU registers and opcodesMax Filippov2020-08-211-23/+1103
* target/xtensa: don't access BR regfile directlyMax Filippov2020-08-211-4/+16
* target/xtensa: move FSR/FCR register accessorsMax Filippov2020-08-211-32/+32
* target/xtensa: rename FPU2000 translators and helpersMax Filippov2020-08-211-35/+35
* target/xtensa: support copying registers up to 64 bits wideMax Filippov2020-08-211-5/+21
* target/xtensa: add geometry to xtensa_get_regfile_by_nameMax Filippov2020-08-211-8/+27
* target/xtensa: make opcode properties more dynamicMax Filippov2020-08-211-261/+277
* target/xtensa: drop gen_io_end callMax Filippov2020-06-221-3/+0Star
* target/xtensa: fix simcall for newer hardwareMax Filippov2020-05-171-3/+6
* target/xtensa: work around missing SR definitionsMax Filippov2020-04-301-14/+34
* target/xtensa: statically allocate xtensa_insnbufs in DisasContextMax Filippov2020-04-081-16/+2Star
* target/xtensa: fix pasto in pfwait.r opcode nameMax Filippov2020-04-081-1/+1
* target/xtensa: add FIXME for translation memory leakAlex Bennée2020-04-071-0/+5
* tcg: Search includes from the project root source directoryPhilippe Mathieu-Daudé2020-01-161-1/+1
* target/xtensa: fix ps.ring use in MPU configsMax Filippov2020-01-061-1/+2
* target/xtensa: fetch code with translator_ldEmilio G. Cota2019-10-281-2/+2
* icount: remove unnecessary gen_io_end callsPavel Dovgalyuk2019-08-201-15/+0Star
* Clean up inclusion of sysemu/sysemu.hMarkus Armbruster2019-08-161-1/+0Star
* semihosting: move semihosting configuration into its own directoryAlex Bennée2019-05-281-1/+1
* Merge remote-tracking branch 'remotes/xtensa/tags/20190520-xtensa' into stagingPeter Maydell2019-05-211-1005/+1942
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| * target/xtensa: implement exclusive access optionMax Filippov2019-05-151-0/+100
| * target/xtensa: implement block prefetch option opcodesMax Filippov2019-05-151-0/+42
| * target/xtensa: implement DIWBUI.P opcodeMax Filippov2019-05-141-0/+10
| * target/xtensa: implement MPU optionMax Filippov2019-05-111-0/+146
| * target/xtensa: add parity/ECC option SRsMax Filippov2019-05-111-0/+162
| * target/xtensa: get rid of centralized SR propertiesMax Filippov2019-05-111-1005/+1482
* | target/xtensa: Use tcg_gen_abs_i32Richard Henderson2019-05-141-8/+1Star
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* tcg: Hoist max_insns computation to tb_gen_codeRichard Henderson2019-04-241-2/+2
* qom/cpu: Simplify how CPUClass:cpu_dump_state() printsMarkus Armbruster2019-04-181-19/+21
* target/xtensa: fix break_dependency for repeated resourcesMax Filippov2019-03-221-1/+0Star
* target/xtensa: implement PREFCTL SRMax Filippov2019-02-281-0/+16
* target/xtensa: prioritize load/store in FLIX bundlesMax Filippov2019-02-281-5/+32
* target/xtensa: break circular register dependenciesMax Filippov2019-02-281-4/+123
* target/xtensa: reorganize access to boolean registersMax Filippov2019-02-281-8/+42
* target/xtensa: reorganize access to MAC16 registersMax Filippov2019-02-281-94/+92Star
* target/xtensa: reorganize register handling in translatorsMax Filippov2019-02-281-341/+359
* target/xtensa: only rotate window in the retw helperMax Filippov2019-02-281-2/+7
* target/xtensa: move WINDOW_BASE SR update to postprocessingMax Filippov2019-02-281-8/+22
* target/xtensa: add generic instruction post-processingMax Filippov2019-02-281-8/+25
* target/xtensa: sort FLIX instruction opcodesMax Filippov2019-02-281-8/+219
* target/xtensa: implement wide branches and loopsMax Filippov2019-02-191-27/+102
* target/xtensa: allow multiple names for single opcodeMax Filippov2019-02-191-56/+44Star
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