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* target/xtensa: fix ps.ring use in MPU configsMax Filippov2020-01-062-4/+9
* target/xtensa: fetch code with translator_ldEmilio G. Cota2019-10-281-2/+2
* target/xtensa: regenerate and re-import test_mmuhifi_c3 coreMax Filippov2019-10-194-3001/+3154
* target/xtensa: linux-user: add call0 ABI supportMax Filippov2019-09-112-4/+23
* Merge remote-tracking branch 'remotes/armbru/tags/pull-monitor-2019-08-21' in...Peter Maydell2019-08-221-1/+1
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| * hw/core: Move cpu.c, cpu.h from qom/ to hw/core/Markus Armbruster2019-08-211-1/+1
* | icount: remove unnecessary gen_io_end callsPavel Dovgalyuk2019-08-201-15/+0Star
* | configure: Define target access alignment in configuretony.nguyen@bt.com2019-08-201-2/+0Star
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* Clean up inclusion of sysemu/sysemu.hMarkus Armbruster2019-08-162-2/+0Star
* hmp: Move hmp.h to include/monitor/Markus Armbruster2019-07-021-1/+1
* Include qemu-common.h exactly where neededMarkus Armbruster2019-06-127-7/+0Star
* Include qemu/module.h where needed, drop it from qemu-common.hMarkus Armbruster2019-06-121-1/+1
* cpu: Remove CPU_COMMONRichard Henderson2019-06-101-2/+0Star
* cpu: Introduce CPUNegativeOffsetStateRichard Henderson2019-06-101-0/+1
* cpu: Introduce cpu_set_cpustate_pointersRichard Henderson2019-06-101-2/+1Star
* cpu: Move ENV_OFFSET to exec/gen-icount.hRichard Henderson2019-06-101-2/+0Star
* target/xtensa: Use env_cpu, env_archcpuRichard Henderson2019-06-106-31/+20Star
* cpu: Replace ENV_GET_CPU with env_cpuRichard Henderson2019-06-101-2/+0Star
* cpu: Define ArchCPURichard Henderson2019-06-101-0/+1
* cpu: Define CPUArchState with typedefRichard Henderson2019-06-101-2/+2
* tcg: Split out target/arch/cpu-param.hRichard Henderson2019-06-102-16/+26
* semihosting: move semihosting configuration into its own directoryAlex Bennée2019-05-282-2/+2
* Merge remote-tracking branch 'remotes/xtensa/tags/20190520-xtensa' into stagingPeter Maydell2019-05-218-1107/+2524
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| * target/xtensa: implement exclusive access optionMax Filippov2019-05-156-2/+152
| * target/xtensa: update list of exception causesMax Filippov2019-05-151-4/+5
| * target/xtensa: implement block prefetch option opcodesMax Filippov2019-05-151-0/+42
| * target/xtensa: implement DIWBUI.P opcodeMax Filippov2019-05-143-0/+12
| * target/xtensa: implement MPU optionMax Filippov2019-05-116-1/+566
| * target/xtensa: add parity/ECC option SRsMax Filippov2019-05-113-0/+170
| * target/xtensa: define IDMA and gather/scatter IRQ typesMax Filippov2019-05-112-0/+6
| * target/xtensa: make internal MMU functions staticMax Filippov2019-05-112-95/+87Star
| * target/xtensa: get rid of centralized SR propertiesMax Filippov2019-05-113-1005/+1484
* | Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20190510' into stagingPeter Maydell2019-05-163-18/+25
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| * | tcg: Use CPUClass::tlb_fill in cputlb.cRichard Henderson2019-05-101-6/+0Star
| * | target/xtensa: Convert to CPUClass::tlb_fillRichard Henderson2019-05-103-18/+31
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* | target/xtensa: Use tcg_gen_abs_i32Richard Henderson2019-05-141-8/+1Star
* | Clean up decorations and whitespace around header guardsMarkus Armbruster2019-05-131-1/+1
* | target/xtensa: Clean up core-isa.h header guardsMarkus Armbruster2019-05-134-20/+12Star
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* tcg: Hoist max_insns computation to tb_gen_codeRichard Henderson2019-04-241-2/+2
* qom/cpu: Simplify how CPUClass:cpu_dump_state() printsMarkus Armbruster2019-04-182-21/+22
* target: Clean up how the dump_mmu() printMarkus Armbruster2019-04-183-15/+13Star
* target: Simplify how the TARGET_cpu_list() printMarkus Armbruster2019-04-182-4/+5
* target/xtensa: don't announce exit simcallMax Filippov2019-03-231-1/+0Star
* target/xtensa: fix break_dependency for repeated resourcesMax Filippov2019-03-221-1/+0Star
* target/xtensa: implement PREFCTL SRMax Filippov2019-02-282-0/+17
* target/xtensa: prioritize load/store in FLIX bundlesMax Filippov2019-02-282-5/+36
* target/xtensa: break circular register dependenciesMax Filippov2019-02-281-4/+123
* target/xtensa: reorganize access to boolean registersMax Filippov2019-02-281-8/+42
* target/xtensa: reorganize access to MAC16 registersMax Filippov2019-02-281-94/+92Star
* target/xtensa: reorganize register handling in translatorsMax Filippov2019-02-283-344/+386
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