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* Merge remote-tracking branch 'remotes/philmd/tags/mips-20210702' into stagingPeter Maydell2021-07-045-9264/+9294
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| * target/mips: Extract nanoMIPS ISA translation routinesPhilippe Mathieu-Daudé2021-07-022-4922/+4924
| * target/mips: Extract the microMIPS ISA translation routinesPhilippe Mathieu-Daudé2021-07-022-3225/+3237
| * target/mips: Extract Code Compaction ASE translation routinesPhilippe Mathieu-Daudé2021-07-022-1117/+1129
| * target/mips: Add declarations for generic TCG helpersPhilippe Mathieu-Daudé2021-07-022-5/+9
* | target/arm: Implement MVE shifts by registerPeter Maydell2021-07-025-4/+57
* | target/arm: Implement MVE shifts by immediatePeter Maydell2021-07-025-10/+105
* | target/arm: Implement MVE long shifts by registerPeter Maydell2021-07-025-3/+182
* | target/arm: Implement MVE long shifts by immediatePeter Maydell2021-07-025-0/+132
* | target/arm: Implement MVE VADDLVPeter Maydell2021-07-024-1/+90
* | target/arm: Implement MVE VSHLCPeter Maydell2021-07-024-0/+72
* | target/arm: Implement MVE saturating narrowing shiftsPeter Maydell2021-07-024-0/+174
* | target/arm: Implement MVE VSHRN, VRSHRNPeter Maydell2021-07-024-0/+76
* | target/arm: Implement MVE VSRI, VSLIPeter Maydell2021-07-024-0/+62
* | target/arm: Implement MVE VSHLLPeter Maydell2021-07-024-4/+105
* | target/arm: Implement MVE vector shift right by immediate insnsPeter Maydell2021-07-026-18/+72
* | target/arm: Implement MVE vector shift left by immediate insnsPeter Maydell2021-07-024-0/+147
* | target/arm: Implement MVE logical immediate insnsPeter Maydell2021-07-024-0/+95
* | target/arm: Use dup_const() instead of bitfield_replicate()Peter Maydell2021-07-021-1/+1
* | target/arm: Use asimd_imm_const for A64 decodePeter Maydell2021-07-023-82/+24Star
* | target/arm: Make asimd_imm_const() publicPeter Maydell2021-07-023-63/+73
* | target/arm: Fix bugs in MVE VRMLALDAVH, VRMLSLDAVHPeter Maydell2021-07-021-17/+21
* | target/arm: Fix MVE widening/narrowing VLDR/VSTR offset calculationPeter Maydell2021-07-021-8/+9
* | target/arm: Check NaN mode before silencing NaNJoe Komlodi2021-07-022-9/+27
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* Merge remote-tracking branch 'remotes/rth-gitlab/tags/pull-tcg-20210629' into...Peter Maydell2021-07-0111-600/+584Star
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| * target/mips: Fix gen_mxu_s32ldd_s32lddrRichard Henderson2021-06-291-5/+1Star
| * target/sh4: Improve swap.b translationRichard Henderson2021-06-291-2/+1Star
| * target/i386: Improve bswap translationRichard Henderson2021-06-291-10/+4Star
| * target/arm: Improve REVSHRichard Henderson2021-06-291-3/+1Star
| * target/arm: Improve vector REVRichard Henderson2021-06-291-4/+2Star
| * target/arm: Improve REV32Richard Henderson2021-06-291-13/+4Star
| * tcg: Add flags argument to tcg_gen_bswap16_*, tcg_gen_bswap32_i64Richard Henderson2021-06-296-11/+13
| * target/cris: Do not exit tb for X_FLAG changesRichard Henderson2021-06-291-3/+0Star
| * target/cris: Remove dc->flagx_knownRichard Henderson2021-06-292-81/+24Star
| * target/cris: Improve JMP_INDIRECTRichard Henderson2021-06-291-12/+10Star
| * target/cris: Use tcg_gen_lookup_and_goto_ptrRichard Henderson2021-06-291-1/+3
| * target/cris: Add DISAS_DBRANCHRichard Henderson2021-06-291-40/+56
| * target/cris: Add DISAS_UPDATE_NEXTRichard Henderson2021-06-291-5/+15
| * target/cris: Set cpustate_changed for rfe/rfnRichard Henderson2021-06-291-0/+2
| * target/cris: Fold unhandled X_FLAG changes into cpustate_changedRichard Henderson2021-06-291-7/+6Star
| * target/cris: Mark static arrays constRichard Henderson2021-06-292-12/+13
| * target/cris: Mark helper_raise_exception noreturnRichard Henderson2021-06-291-1/+1
| * target/cris: Convert to TranslatorOpsRichard Henderson2021-06-291-138/+169
| * target/cris: Fix use_goto_tbRichard Henderson2021-06-291-7/+2Star
| * target/cris: Mark exceptions as DISAS_NORETURNRichard Henderson2021-06-292-3/+5
| * target/cris: Replace DISAS_TB_JUMP with DISAS_NORETURNRichard Henderson2021-06-291-4/+3Star
| * target/cris: Remove DISAS_SWIRichard Henderson2021-06-291-2/+0Star
| * target/cris: Add DisasContextBase to DisasContextRichard Henderson2021-06-292-26/+27
| * target/avr: Convert to TranslatorOpsRichard Henderson2021-06-291-104/+126
| * target/avr: Change ctx to DisasContext* in gen_intermediate_codeRichard Henderson2021-06-291-41/+43
generated by cgit v1.2.3-55-g7522 (git 2.39.0) at 2024-12-12 07:26:44 +0100