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* Merge remote-tracking branch 'remotes/mst/tags/for_upstream' into stagingPeter Maydell2020-07-071-0/+7
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| * target/i386: sev: Use ram_block_discard_disable()David Hildenbrand2020-07-021-0/+7
* | Merge remote-tracking branch 'remotes/vivier2/tags/linux-user-for-5.1-pull-re...Peter Maydell2020-07-061-0/+2
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| * | target/sparc: Translate flushw opcodeGiuseppe Musacchio2020-06-291-0/+2
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* | Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20200703'...Peter Maydell2020-07-048-6/+184
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| * | target/arm: Fix temp double-free in sve ldr/strRichard Henderson2020-07-033-6/+9
| * | target/arm: kvm: Handle misconfigured dabt injectionBeata Michalska2020-07-035-1/+124
| * | target/arm: kvm: Handle DABT with no valid ISSBeata Michalska2020-07-031-0/+52
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* | Merge remote-tracking branch 'remotes/cohuck/tags/s390x-20200703' into stagingPeter Maydell2020-07-041-1/+1
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| * | target/s390x: Fix SQXBRRichard Henderson2020-07-031-1/+1
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* | target/riscv: configure and turn on vector extension from command lineLIU Zhiwei2020-07-022-1/+46
* | target/riscv: vector compress instructionLIU Zhiwei2020-07-024-0/+64
* | target/riscv: vector register gather instructionLIU Zhiwei2020-07-024-0/+150
* | target/riscv: vector slide instructionsLIU Zhiwei2020-07-024-0/+155
* | target/riscv: floating-point scalar move instructionsLIU Zhiwei2020-07-022-0/+52
* | target/riscv: integer scalar move instructionLIU Zhiwei2020-07-023-0/+67
* | target/riscv: integer extract instructionLIU Zhiwei2020-07-022-0/+117
* | target/riscv: vector element index instructionLIU Zhiwei2020-07-024-0/+56
* | target/riscv: vector iota instructionLIU Zhiwei2020-07-024-0/+62
* | target/riscv: set-X-first mask bitLIU Zhiwei2020-07-024-0/+98
* | target/riscv: vmfirst find-first-set mask bitLIU Zhiwei2020-07-024-0/+54
* | target/riscv: vector mask population count vmpopcLIU Zhiwei2020-07-024-0/+55
* | target/riscv: vector mask-register logical instructionsLIU Zhiwei2020-07-024-0/+92
* | target/riscv: vector widening floating-point reduction instructionsLIU Zhiwei2020-07-024-0/+54
* | target/riscv: vector single-width floating-point reduction instructionsLIU Zhiwei2020-07-024-0/+58
* | target/riscv: vector wideing integer reduction instructionsLIU Zhiwei2020-07-024-0/+24
* | target/riscv: vector single-width integer reduction instructionsLIU Zhiwei2020-07-024-0/+133
* | target/riscv: narrowing floating-point/integer type-convert instructionsLIU Zhiwei2020-07-024-0/+103
* | target/riscv: widening floating-point/integer type-convert instructionsLIU Zhiwei2020-07-024-0/+106
* | target/riscv: vector floating-point/integer type-convert instructionsLIU Zhiwei2020-07-024-0/+56
* | target/riscv: vector floating-point merge instructionsLIU Zhiwei2020-07-024-0/+68
* | target/riscv: vector floating-point classify instructionsLIU Zhiwei2020-07-026-30/+107
* | target/riscv: vector floating-point compare instructionsLIU Zhiwei2020-07-024-0/+258
* | target/riscv: vector floating-point sign-injection instructionsLIU Zhiwei2020-07-024-0/+118
* | target/riscv: vector floating-point min/max instructionsLIU Zhiwei2020-07-024-0/+50
* | target/riscv: vector floating-point square-root instructionLIU Zhiwei2020-07-024-0/+93
* | target/riscv: vector widening floating-point fused multiply-add instructionsLIU Zhiwei2020-07-024-0/+126
* | target/riscv: vector single-width floating-point fused multiply-add instructionsLIU Zhiwei2020-07-024-0/+334
* | target/riscv: vector widening floating-point multiplyLIU Zhiwei2020-07-024-0/+33
* | target/riscv: vector single-width floating-point multiply/divide instructionsLIU Zhiwei2020-07-024-0/+77
* | target/riscv: vector widening floating-point add/subtract instructionsLIU Zhiwei2020-07-024-0/+257
* | target/riscv: vector single-width floating-point add/subtract instructionsLIU Zhiwei2020-07-024-0/+250
* | target/riscv: vector narrowing fixed-point clip instructionsLIU Zhiwei2020-07-024-0/+168
* | target/riscv: vector single-width scaling shift instructionsLIU Zhiwei2020-07-024-0/+148
* | target/riscv: vector widening saturating scaled multiply-addLIU Zhiwei2020-07-024-0/+243
* | target/riscv: vector single-width fractional multiply with rounding and satur...LIU Zhiwei2020-07-024-0/+122
* | target/riscv: vector single-width averaging add and subtractLIU Zhiwei2020-07-024-0/+129
* | target/riscv: vector single-width saturating add and subtractLIU Zhiwei2020-07-024-0/+444
* | target/riscv: vector integer merge and move instructionsLIU Zhiwei2020-07-024-0/+225
* | target/riscv: vector widening integer multiply-add instructionsLIU Zhiwei2020-07-024-0/+83
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