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* migration: disallow migrate_add_blocker during migrationAshijeet Acharya2017-01-241-3/+13
| | | | | | | | | | | | | | | If a migration is already in progress and somebody attempts to add a migration blocker, this should rightly fail. Add an errp parameter and a retcode return value to migrate_add_blocker. Signed-off-by: John Snow <jsnow@redhat.com> Signed-off-by: Ashijeet Acharya <ashijeetacharya@gmail.com> Message-Id: <1484566314-3987-5-git-send-email-ashijeetacharya@gmail.com> Reviewed-by: Dr. David Alan Gilbert <dgilbert@redhat.com> Acked-by: Greg Kurz <groug@kaod.org> Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com> Merged with recent 'Allow invtsc migration' change
* migration: extend VMStateInfoJianjun Duan2017-01-246-23/+55
| | | | | | | | | | | | | Current migration code cannot handle some data structures such as QTAILQ in qemu/queue.h. Here we extend the signatures of put/get in VMStateInfo so that customized handling is supported. put now will return int type. Reviewed-by: Dr. David Alan Gilbert <dgilbert@redhat.com> Signed-off-by: Jianjun Duan <duanj@linux.vnet.ibm.com> Message-Id: <1484852453-12728-2-git-send-email-duanj@linux.vnet.ibm.com> Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
* Merge remote-tracking branch ↵Peter Maydell2017-01-244-44/+30Star
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 'remotes/ehabkost/tags/x86-and-machine-pull-request' into staging x86, machine, numa queue (2017-01-23) # gpg: Signature made Mon 23 Jan 2017 23:26:59 GMT # gpg: using RSA key 0x2807936F984DC5A6 # gpg: Good signature from "Eduardo Habkost <ehabkost@redhat.com>" # Primary key fingerprint: 5A32 2FD5 ABC4 D3DB ACCF D1AA 2807 936F 984D C5A6 * remotes/ehabkost/tags/x86-and-machine-pull-request: kvm: Allow invtsc migration if tsc-khz is set explicitly kvm: Simplify invtsc check hw/core/null-machine: Add the possibility to instantiate a CPU and RAM qemu-options: Rename variables on the -numa "cpus" option MAINTAINERS: Add an entry for hw/core/null-machine.c machine: Make possible_cpu_arch_ids() return const pointer pc: don't return cpu pointer from pc_new_cpu() as it's not needed anymore pc: cleanup: move smbios_set_cpuid() into pc_build_smbios() arch_init: Remove unnecessary default_config_files table vl: Ensure the numa_post_machine_init func in the appropriate location i386: Return migration-safe field on query-cpu-definitions i386: Remove AMD feature flag aliases from Opteron models x86: add AVX512_VPOPCNTDQ features Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * kvm: Allow invtsc migration if tsc-khz is set explicitlyEduardo Habkost2017-01-241-9/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | We can safely allow a VM to be migrated with invtsc enabled if tsc-khz is set explicitly, because: * QEMU already refuses to start if it can't set the TSC frequency to the configured value. * Management software is already required to keep device configuration (including CPU configuration) the same on migration source and destination. Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Message-Id: <20170108173234.25721-3-ehabkost@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
| * kvm: Simplify invtsc checkEduardo Habkost2017-01-241-2/+2
| | | | | | | | | | | | | | | | | | | | Instead of searching the table we have just built, we can check the env->features field directly. Reviewed-by: Marcelo Tosatti <mtosatti@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Message-Id: <20170108173234.25721-2-ehabkost@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
| * i386: Return migration-safe field on query-cpu-definitionsEduardo Habkost2017-01-242-0/+5
| | | | | | | | | | | | | | | | | | | | Return the migration-safe field on query-cpu-definitions. All CPU models in x86 are migration-safe except "host". Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Message-Id: <20170116181212.31565-1-ehabkost@redhat.com> Acked-by: David Hildenbrand <david@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
| * i386: Remove AMD feature flag aliases from Opteron modelsEduardo Habkost2017-01-241-34/+12Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When CPU vendor is set to AMD, the AMD feature alias bits on CPUID[0x80000001].EDX are already automatically copied from CPUID[1].EDX on x86_cpu_realizefn(). When CPU vendor is Intel, those bits are reserved and should be zero. On either case, those bits shouldn't be set in the CPU model table. Commit 726a8ff68677d8d5fba17eb0ffb85076bfb598dc removed those bits from most CPU models, but the Opteron_* entries still have them. Remove the alias bits from Opteron_* too. Add an assert() to x86_register_cpudef_type() to ensure we don't make the same mistake again. Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Message-Id: <20170113190057.6327-1-ehabkost@redhat.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
| * x86: add AVX512_VPOPCNTDQ featuresHe Chen2017-01-242-1/+2
| | | | | | | | | | | | | | | | | | | | AVX512_VPOPCNTDQ: Vector POPCNT instructions for word and qwords. variable precision. Signed-off-by: He Chen <he.chen@linux.intel.com> Message-Id: <1484272411-28073-1-git-send-email-he.chen@linux.intel.com> Reviewed-by: Eduardo Habkost <ehabkost@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
* | Merge remote-tracking branch 'remotes/rth/tags/pull-hppa-20170123' into stagingPeter Maydell2017-01-249-0/+5191
|\ \ | |/ |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | hppa-linux target support # gpg: Signature made Mon 23 Jan 2017 17:54:09 GMT # gpg: using RSA key 0xAD1270CC4DD0279B # gpg: Good signature from "Richard Henderson <rth7680@gmail.com>" # gpg: aka "Richard Henderson <rth@redhat.com>" # gpg: aka "Richard Henderson <rth@twiddle.net>" # Primary key fingerprint: 9CB1 8DDA F8E8 49AD 2AFC 16A4 AD12 70CC 4DD0 279B * remotes/rth/tags/pull-hppa-20170123: (25 commits) target-hppa: Implement floating-point insns target-hppa: Implement system and memory-management insns target-hppa: Implement loads and stores target-hppa: Implement shifts and deposits target-hppa: Implement linux-user gateway page target-hppa: Implement branches target-hppa: Implement basic arithmetic target-hppa: Add nullification framework target-hppa: Add framework and enable compilation target-hppa: Add softfloat specializations linux-user: Add HPPA startup and main loop linux-user: Add HPPA signal handling linux-user: Add HPPA target_signal.h and target_cpu.h linux-user: Add HPPA target_structs.h linux-user: Add HPPA definitions to syscall_defs.h linux-user: Add HPPA target_syscall.h linux-user: Add HPPA termbits.h linux-user: Add HPPA syscall numbers linux-user: Add HPPA socket.h definitions linux-user: Add some hppa ioctls ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * target-hppa: Implement floating-point insnsRichard Henderson2017-01-233-0/+1177
| | | | | | | | Signed-off-by: Richard Henderson <rth@twiddle.net>
| * target-hppa: Implement system and memory-management insnsRichard Henderson2017-01-233-0/+219
| | | | | | | | Signed-off-by: Richard Henderson <rth@twiddle.net>
| * target-hppa: Implement loads and storesRichard Henderson2017-01-233-0/+699
| | | | | | | | Signed-off-by: Richard Henderson <rth@twiddle.net>
| * target-hppa: Implement shifts and depositsRichard Henderson2017-01-231-0/+309
| | | | | | | | Signed-off-by: Richard Henderson <rth@twiddle.net>
| * target-hppa: Implement linux-user gateway pageRichard Henderson2017-01-231-4/+81
| | | | | | | | | | | | | | | | | | | | | | | | For linux, page 0 is mapped as an execute-only gateway. A gateway page is a special bit in the page table that allows a B,GATE insn within that page to raise processor permissions. This is how system calls are implemented for HPPA. Rather than actually map anything here, or handle permissions at all, implement the semantics of the actual linux syscall entry points. Signed-off-by: Richard Henderson <rth@twiddle.net>
| * target-hppa: Implement branchesRichard Henderson2017-01-231-0/+477
| | | | | | | | Signed-off-by: Richard Henderson <rth@twiddle.net>
| * target-hppa: Implement basic arithmeticRichard Henderson2017-01-233-0/+907
| | | | | | | | Signed-off-by: Richard Henderson <rth@twiddle.net>
| * target-hppa: Add nullification frameworkRichard Henderson2017-01-231-4/+224
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The HPPA cpu has a unique form of predicated execution in which almost any instruction can set the PSW[N] (or "nullify") bit, which suppresses execution (and even decoding) of the following instruction. Execution of a nullified insn clears the PSW[N] bit. This adds a generic framework for branching over nullified insns, or for sufficiently simple insns, transforming the writeback of the result to a conditional move. In the process, we want to be able to represent PSW[N] as a TCG condition, which implies management of the related tcg temps. Signed-off-by: Richard Henderson <rth@twiddle.net>
| * target-hppa: Add framework and enable compilationRichard Henderson2017-01-239-0/+1106
| | | | | | | | | | | | | | | | | | | | This is just about the minimum required to enable compilation without actually executing any instructions. This contains the HPPACPU structure and the required callbacks, the gdbstub, the basic translation loop, and a translate_one function that always results in an illegal instruction. Signed-off-by: Richard Henderson <rth@twiddle.net>
* | Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into stagingPeter Maydell2017-01-2020-19/+2879
|\ \ | |/ |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * QOM interface fix (Eduardo) * RTC fixes (Gaohuai, Igor) * Memory leak fixes (Li Qiang, me) * Ctrl-a b regression (Marc-André) * Stubs cleanups and fixes (Leif, me) * hxtool tweak (me) * HAX support (Vincent) * QemuThread, exec.c and SCSI fixes (Roman, Xinhua, me) * PC_COMPAT_2_8 fix (Marcelo) * stronger bitmap assertions (Peter) # gpg: Signature made Fri 20 Jan 2017 12:49:01 GMT # gpg: using RSA key 0xBFFBD25F78C7AE83 # gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" # gpg: aka "Paolo Bonzini <pbonzini@redhat.com>" # Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4 E2F7 7E15 100C CD36 69B1 # Subkey fingerprint: F133 3857 4B66 2389 866C 7682 BFFB D25F 78C7 AE83 * remotes/bonzini/tags/for-upstream: (35 commits) pc.h: move x-mach-use-reliable-get-clock compat entry to PC_COMPAT_2_8 bitmap: assert that start and nr are non negative Revert "win32: don't run subprocess tests on Mingw32 platform" hax: add Darwin support Plumb the HAXM-based hardware acceleration support target/i386: Add Intel HAX files kvm: move cpu synchronization code KVM: PPC: eliminate unnecessary duplicate constants ramblock-notifier: new char: fix ctrl-a b not working exec: Add missing rcu_read_unlock x86: ioapic: fix fail migration when irqchip=split x86: ioapic: dump version for "info ioapic" x86: ioapic: add traces for ioapic hxtool: emit Texinfo headings as @subsection qemu-thread: fix qemu_thread_set_name() race in qemu_thread_create() serial: fix memory leak in serial exit scsi-block: fix direction of BYTCHK test for VERIFY commands pc: fix crash in rtc_set_memory() if initial cpu is marked as hotplugged acpi: filter based on CONFIG_ACPI_X86 rather than TARGET ... # Conflicts: # include/hw/i386/pc.h
| * hax: add Darwin supportVincent Palatin2017-01-194-0/+390
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Re-add the MacOSX/Darwin support: Use the Intel HAX is kernel-based hardware acceleration module (similar to KVM on Linux). Based on the original "target/i386: Add Intel HAX to android emulator" patch from David Chou <david.j.chou@intel.com> from emu-2.2-release branch in the external/qemu-android repository. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> Message-Id: <81b85c3032da902e73e77302af508b4b1a7c0ead.1484045952.git.vpalatin@chromium.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
| * Plumb the HAXM-based hardware acceleration supportVincent Palatin2017-01-191-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | Use the Intel HAX is kernel-based hardware acceleration module for Windows (similar to KVM on Linux). Based on the "target/i386: Add Intel HAX to android emulator" patch from David Chou <david.j.chou@intel.com> Signed-off-by: Vincent Palatin <vpalatin@chromium.org> Message-Id: <7b9cae28a0c379ab459c7a8545c9a39762bd394f.1484045952.git.vpalatin@chromium.org> [Drop hax_populate_ram stub. - Paolo] Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
| * target/i386: Add Intel HAX filesVincent Palatin2017-01-196-0/+2459
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | That's a forward port of the core HAX interface code from the emu-2.2-release branch in the external/qemu-android repository as used by the Android emulator. The original commit was "target/i386: Add Intel HAX to android emulator" saying: """ Backport of 2b3098ff27bab079caab9b46b58546b5036f5c0c from studio-1.4-dev into emu-master-dev Intel HAX (harware acceleration) will enhance android emulator performance in Windows and Mac OS X in the systems powered by Intel processors with "Intel Hardware Accelerated Execution Manager" package installed when user runs android emulator with Intel target. Signed-off-by: David Chou <david.j.chou@intel.com> """ It has been modified to build and run along with the current code base. The formatting has been fixed to go through scripts/checkpatch.pl, and the DPRINTF macros have been updated to get the instanciations checked by the compiler. The FPU registers saving/restoring has been updated to match the current QEMU registers layout. The implementation has been simplified by doing the following modifications: - removing the code for supporting the hardware without Unrestricted Guest (UG) mode (including all the code to fallback on TCG emulation). - not including the Darwin support (which is not yet debugged/tested). - simplifying the initialization by removing the leftovers from the Android specific code, then trimming down the remaining logic. - removing the unused MemoryListener callbacks. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> Message-Id: <e1023837f8d0e4c470f6c4a3bf643971b2bca5be.1484045952.git.vpalatin@chromium.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
| * kvm: move cpu synchronization codeVincent Palatin2017-01-197-4/+7
| | | | | | | | | | | | | | | | | | | | Move the generic cpu_synchronize_ functions to the common hw_accel.h header, in order to prepare for the addition of a second hardware accelerator. Signed-off-by: Stefan Weil <sw@weilnetz.de> Signed-off-by: Vincent Palatin <vpalatin@chromium.org> Message-Id: <f5c3cffe8d520011df1c2e5437bb814989b48332.1484045952.git.vpalatin@chromium.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
| * KVM: PPC: eliminate unnecessary duplicate constantsPaolo Bonzini2017-01-191-12/+0Star
| | | | | | | | | | | | | | | | | | | | These are not needed since linux-headers/ provides up-to-date definitions. The constants are in linux-headers/asm-powerpc/kvm.h. The sole users, hw/intc/xics_kvm.c and target/ppc/kvm.c, include asm/kvm.h via sysemu/kvm.h->linux/kvm.h. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
| * stubs: remove stubs/kvm.cPaolo Bonzini2017-01-163-0/+15
| | | | | | | | | | | | This has a single function, just move it to the other target/*/kvm.c files. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
| * event_notifier: cleanups around event_notifier_set_handlerPaolo Bonzini2017-01-161-3/+4
| | | | | | | | | | | | | | | | Remove the useless is_external argument. Since the iohandler AioContext is never used for block devices, aio_disable_external is never called on it. This lets us remove stubs/iohandler.c. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* | Merge remote-tracking branch 'remotes/cohuck/tags/s390x-20170120-v2' into ↵Peter Maydell2017-01-201-1/+1
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | staging First set of s390x patches for 2.9: - rework of the zpci code, giving us proper multibus support - introduction of the 2.9 machine - fixes and improvements # gpg: Signature made Fri 20 Jan 2017 09:11:58 GMT # gpg: using RSA key 0xDECF6B93C6F02FAF # gpg: Good signature from "Cornelia Huck <huckc@linux.vnet.ibm.com>" # gpg: aka "Cornelia Huck <cornelia.huck@de.ibm.com>" # Primary key fingerprint: C3D0 D66D C362 4FF6 A8C0 18CE DECF 6B93 C6F0 2FAF * remotes/cohuck/tags/s390x-20170120-v2: virtio-ccw: fix ring sizing s390x/pci: merge msix init functions s390x/pci: handle PCIBridge bus number s390x/pci: use hashtable to look up zpci via fh s390x/pci: PCI multibus bridge handling s390x/pci: optimize calling s390_get_phb() s390x/pci: change the device array to a list s390x/pci: dynamically allocate iommu s390x/pci: make S390PCIIOMMU inherit Object s390x/kvm: use kvm_gsi_routing_enabled in flic s390x: add compat machine for 2.9 s390x: remove double compat statement Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * | s390x/pci: optimize calling s390_get_phb()Yi Min Zhao2017-01-201-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A function may recursively call device search functions or may call serveral different device search function. Passing the S390pciState to search functions as an argument instead of looking up it inside the search functions lowers the number of calling s390_get_phb(). Signed-off-by: Yi Min Zhao <zyimin@linux.vnet.ibm.com> Reviewed-by: Pierre Morel <pmorel@linux.vnet.ibm.com> Signed-off-by: Cornelia Huck <cornelia.huck@de.ibm.com>
* | | target-arm: Enable EL2 feature bit on A53 and A57Peter Maydell2017-01-203-0/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable the ARM_FEATURE_EL2 bit on Cortex-A52 and Cortex-A57, since this is all now sufficiently implemented to work with the GICv3. We provide the usual CPU property to disable it for backwards compatibility with the older virt boards. In this commit, we disable the EL2 feature on the virt and ZynpMP boards, so there is no overall effect. Another commit will expose a board-level property to allow the user to enable EL2. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Andrew Jones <drjones@redhat.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Alistair Francis <alistair.francis@xilinx.com> Message-id: 1483977924-14522-18-git-send-email-peter.maydell@linaro.org
* | | target/arm/psci.c: If EL2 implemented, start CPUs in EL2Peter Maydell2017-01-201-7/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The PSCI spec states that a CPU_ON call should cause the new CPU to be started in the highest implemented Non-secure exception level. We were incorrectly starting it at the exception level of the caller, which happens to be correct if EL2 is not implemented. Implement the correct logic as described in the PSCI 1.0 spec section 6.4: * if EL2 exists and SCR_EL3.HCE is set: start in EL2 * otherwise start in EL1 Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Andrew Jones <drjones@redhat.com> Tested-by: Andrew Jones <drjones@redhat.com> Message-id: 1483977924-14522-17-git-send-email-peter.maydell@linaro.org
* | | target-arm: Add ARMCPU fields for GIC CPU i/f configPeter Maydell2017-01-202-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add fields to the ARMCPU structure to allow CPU classes to specify the configurable aspects of their GIC CPU interface. In particular, the virtualization support allows different values for number of list registers, priority bits and preemption bits. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Acked-by: Alistair Francis <alistair.francis@xilinx.com> Message-id: 1483977924-14522-6-git-send-email-peter.maydell@linaro.org
* | | target-arm: Expose output GPIO line for VCPU maintenance interruptPeter Maydell2017-01-202-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The GICv3 support for virtualization includes an outbound maintenance interrupt signal which is asserted when the CPU interface wants to signal to the hypervisor that it needs attention. Expose this as an outbound GPIO line from the CPU object which can be wired up as a physical interrupt line by the board code (as we do already for the CPU timers). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Alistair Francis <alistair.francis@xilinx.com> Message-id: 1483977924-14522-4-git-send-email-peter.maydell@linaro.org
* | | target/arm: Implement DBGVCR32_EL2 system registerPeter Maydell2017-01-201-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The DBGVCR_EL2 system register is needed to run a 32-bit EL1 guest under a Linux EL2 64-bit hypervisor. Its only purpose is to provide AArch64 with access to the state of the DBGVCR AArch32 register. Since we only have a dummy DBGVCR, implement a corresponding dummy DBGVCR32_EL2. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
* | | target/arm: Handle VIRQ and VFIQ in arm_cpu_do_interrupt_aarch32()Peter Maydell2017-01-201-0/+14
|/ / | | | | | | | | | | | | | | | | | | To run a VM in 32-bit EL1 our AArch32 interrupt handling code needs to be able to cope with VIRQ and VFIQ exceptions. These behave like IRQ and FIQ except that we don't need to try to route them to Monitor mode. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
* | target-sparc: add ST_BLKINIT_ ASIs for UA2005+ CPUsArtyom Tarasenko2017-01-181-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | In OpenSPARC T1+ TWINX ASIs in store instructions are aliased with Block Initializing Store ASIs. "UltraSPARC T1 Supplement Draft D2.1, 14 May 2007" describes them in the chapter "5.9 Block Initializing Store ASIs" Integer stores of all sizes are allowed with these ASIs. Signed-off-by: Artyom Tarasenko <atar4qemu@gmail.com>
* | target-sparc: store the UA2005 entries in sun4u formatArtyom Tarasenko2017-01-182-8/+47
| | | | | | | | | | | | | | | | | | | | According to chapter 13.3 of the UltraSPARC T1 Supplement to the UltraSPARC Architecture 2005, only the sun4u format is available for data-access loads. Store UA2005 entries in the sun4u format to simplify processing. Signed-off-by: Artyom Tarasenko <atar4qemu@gmail.com>
* | target-sparc: implement UA2005 ASI_MMU (0x21)Artyom Tarasenko2017-01-181-0/+31
| | | | | | | | Signed-off-by: Artyom Tarasenko <atar4qemu@gmail.com>
* | target-sparc: add more registers to dump_mmuArtyom Tarasenko2017-01-181-0/+2
| | | | | | | | | | Signed-off-by: Artyom Tarasenko <atar4qemu@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net>
* | target-sparc: implement auto-demapping for UA2005 CPUsArtyom Tarasenko2017-01-181-0/+22
| | | | | | | | Signed-off-by: Artyom Tarasenko <atar4qemu@gmail.com>
* | target-sparc: allow 256M sized pagesArtyom Tarasenko2017-01-181-17/+1Star
| | | | | | | | Signed-off-by: Artyom Tarasenko <atar4qemu@gmail.com>
* | target-sparc: simplify ultrasparc_tsb_pointerArtyom Tarasenko2017-01-181-36/+15Star
| | | | | | | | Signed-off-by: Artyom Tarasenko <atar4qemu@gmail.com>
* | target-sparc: implement UA2005 TSB PointersArtyom Tarasenko2017-01-182-22/+104
| | | | | | | | Signed-off-by: Artyom Tarasenko <atar4qemu@gmail.com>
* | target-sparc: use SparcV9MMU type for sparc64 I/D-MMUsArtyom Tarasenko2017-01-183-36/+24Star
| | | | | | | | Signed-off-by: Artyom Tarasenko <atar4qemu@gmail.com>
* | target-sparc: replace the last tlb entry when no free entries leftArtyom Tarasenko2017-01-181-2/+4
| | | | | | | | | | | | | | | | | | | | | | Implement the behavior described in the chapter 13.9.11 of UltraSPARC T1™ Supplement to the UltraSPARC Architecture 2005: "If a TLB Data-In replacement is attempted with all TLB entries locked and valid, the last TLB entry (entry 63) is replaced." Signed-off-by: Artyom Tarasenko <atar4qemu@gmail.com>
* | target-sparc: ignore writes to UA2005 CPU mondo queue registerArtyom Tarasenko2017-01-181-0/+1
| | | | | | | | | | Signed-off-by: Artyom Tarasenko <atar4qemu@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net>
* | target-sparc: allow priveleged ASIs in hyperprivileged modeArtyom Tarasenko2017-01-181-14/+18
| | | | | | | | Signed-off-by: Artyom Tarasenko <atar4qemu@gmail.com>
* | target-sparc: use direct address translation in hyperprivileged modeArtyom Tarasenko2017-01-182-5/+4Star
| | | | | | | | | | | | | | | | Please note that QEMU doesn't impelement Real->Physical address translation. The "Real Address" is always the "Physical Address". Suggested-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Artyom Tarasenko <atar4qemu@gmail.com>
* | target-sparc: fix immediate UA2005 trapsArtyom Tarasenko2017-01-181-1/+1
| | | | | | | | Signed-off-by: Artyom Tarasenko <atar4qemu@gmail.com>
* | target-sparc: implement UA2005 rdhpstate and wrhpstate instructionsArtyom Tarasenko2017-01-181-2/+5
| | | | | | | | | | Signed-off-by: Artyom Tarasenko <atar4qemu@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net>
* | target-sparc: implement UA2005 GL registerArtyom Tarasenko2017-01-186-7/+58
| | | | | | | | Signed-off-by: Artyom Tarasenko <atar4qemu@gmail.com>