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* target/s390x: cleanup cpu.hDavid Hildenbrand2017-08-301-69/+68Star
| | | | | | | | | | | Let's reshuffle the function prototypes so we get a cleaner outline of the files. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20170818114353.13455-19-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
* s390x/kvm: move KVM declarations and stubs to separate filesDavid Hildenbrand2017-08-3010-119/+167
| | | | | | | | | | | | | | | Let's do it just like the other architectures. Introduce kvm-stub.c for stubs and kvm_s390x.h for the declarations. Change license to GPL2+ and keep copyright notice. As we are dropping the sysemu/kvm.h include from cpu.h, fix up includes. Suggested-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20170818114353.13455-18-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
* s390x: avoid calling kvm_ functions outside of target/s390x/David Hildenbrand2017-08-302-0/+8
| | | | | | | | | | | Let's just introduce an helper. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20170818114353.13455-17-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
* target/s390x: move a couple of functions to cpu.cDavid Hildenbrand2017-08-302-79/+89
| | | | | | | | | | | | Prepare to move more stuff (especially KVM related) from cpu.h to internal.h. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20170818114353.13455-16-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
* target/s390x: introduce internal.hDavid Hildenbrand2017-08-3020-343/+409
| | | | | | | | | | | | | | | | | | | | | | | | cpu.h should only contain what really has to be accessed outside of target/s390x/. Add internal.h which can only be used inside target/s390x/. Move everything that isn't fast enough to run away and restructure it right away. We'll move all kvm_* stuff later. Minor style fixes to avoid checkpatch warning to: - struct Lowcore: "{" goes into same line as typedef - struct LowCore: add spaces around "-" in array length calculations - time2tod() and tod2time(): move "{" to separate line - get_per_atmid(): add space between ")" and "?". Move cases by one char. - get_per_atmid(): drop extra paremthesis around (1 << 6) Change license of new file to GPL2+ and keep copyright notice. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20170818114353.13455-15-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
* target/s390x: move get_per_in_range() to misc_helper.cDavid Hildenbrand2017-08-302-11/+11
| | | | | | | | | | | Only used in that file. Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20170818114353.13455-14-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
* target/s390x: move s390_do_cpu_reset() to diag.cDavid Hildenbrand2017-08-302-7/+7
| | | | | | | | | | | Only used in that file. Also drop the comment, not really needed. Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20170818114353.13455-13-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
* target/s390x: move psw_key_valid() to mem_helper.cDavid Hildenbrand2017-08-302-11/+11
| | | | | | | | | | | Only used in that file. Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20170818114353.13455-12-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
* target/s390x: move cpu_mmu_idx_to_asc() to excp_helper.cDavid Hildenbrand2017-08-302-14/+14
| | | | | | | | | | | Only used in that file. Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20170818114353.13455-11-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
* target/s390x: move cc_name() to helper.cDavid Hildenbrand2017-08-302-47/+49
| | | | | | | | | | | | | While at it, move the translations into the function and properly pass enum cc_op as parameter. We can't move it to cc_helper.c as this would break --disable-tcg. Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20170818114353.13455-10-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
* target/s390x: move gtod_*() declarations to s390-virtio.hDavid Hildenbrand2017-08-301-3/+0Star
| | | | | | | | | | The functions are not used in target/s390x/ so a header in hw/s390x/ is a better place. Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20170818114353.13455-9-david@redhat.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
* s390x: drop inclusion of sysemu/kvm.h from some filesDavid Hildenbrand2017-08-301-1/+0Star
| | | | | | | | s390-stattrib.c needs definition of TARGET_PAGE_SIZE, solve it via cpu.h. Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20170818114353.13455-8-david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
* s390x/cpumodel: factor out determination of default model nameDavid Hildenbrand2017-08-302-0/+9
| | | | | | | | | Now we can drop inclusion of "sysemu/kvm.h" from "s390-virtio.c". Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20170818114353.13455-7-david@redhat.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
* s390x/kvm: drop KVMState parameter from kvm_s390_set_mem_limit()David Hildenbrand2017-08-302-10/+9Star
| | | | | | | | | | Not needed at that point. Also drop it from kvm_s390_query_mem_limit() we call in kvm_s390_set_mem_limit(). Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20170818114353.13455-3-david@redhat.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
* s390x/kvm: drop KVMState parameter from s390_get_memslot_count()David Hildenbrand2017-08-302-6/+6
| | | | | | | | | Not needed at that point. Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20170818114353.13455-2-david@redhat.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
* s390x/pci: fence off instructions for non-pciCornelia Huck2017-08-301-13/+41
| | | | | | | | | | If a guest running on a machine without zpci issues a pci instruction, throw them an exception. Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Halil Pasic <pasic@linux.vnet.ibm.com> Acked-by: Christian Borntraeger <borntraeger@de.ibm.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
* s390x/pci: do not advertise pci on non-pci buildsCornelia Huck2017-08-301-1/+3
| | | | | | | | | Only set the zpci feature bit on builds that actually support pci. Reviewed-by: David Hildenbrand <david@redhat.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Acked-by: Christian Borntraeger <borntraeger@de.ibm.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
* s390x: chsc nt2 events are pci-onlyCornelia Huck2017-08-301-0/+16
| | | | | | | | | The nt2 event class is pci-only - don't look for events if pci is not in the active cpu model. Reviewed-by: Thomas Huth <thuth@redhat.com> Acked-by: Christian Borntraeger <borntraeger@de.ibm.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
* s390x: wire up diag288 in tcgCornelia Huck2017-08-301-0/+4
| | | | | | | Make the diag288 watchdog useable via tcg as well. Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
* s390x/tcg: specification exception for unknown diagCornelia Huck2017-08-301-1/+1
| | | | | | | | | | While the PoP is silent on the issue, z/VM documentation states that unknown diagnose codes trigger a specification exception. We already do that when running with kvm, so change tcg to do so as well. Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
* ppc: fix ppc_set_compat() with KVM PRGreg Kurz2017-08-221-4/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | When running in KVM PR mode, kvmppc_set_compat() always fail because the current PR implementation doesn't handle KVM_REG_PPC_ARCH_COMPAT. Now that the machine code inconditionally calls ppc_set_compat_all() at reset time to restore the compat mode default value (commit 66d5c492dd3a9), it is impossible to start a guest with PR: qemu-system-ppc64: Unable to set CPU compatibility mode in KVM: Invalid argument A tentative patch [1] was recently sent by Suraj to address the issue, but it would prevent the compat mode to be turned off on reset. And we really don't want to explicitely check for KVM PR. During the patch's review, David suggested that we should only call the KVM ioctl() if the compat PVR changes. This allows at least to run with KVM PR, provided no compat mode is requested from the command line (which should be the case when running PR nested). This is what this patch does. While here, we also fix the side effect where KVM would fail but we would change the CPU state in QEMU anyway. [1] http://patchwork.ozlabs.org/patch/782039/ Signed-off-by: Greg Kurz <groug@kaod.org> Reviewed-by: Suraj Jitindar Singh <sjitindarsingh@gmail.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
* target/ppc: 'PVR != host PVR' in KVM_SET_SREGS workaroundDaniel Henrique Barboza2017-08-223-0/+61
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit d5fc133eed ("ppc: Rework CPU compatibility testing across migration") changed the way cpu_post_load behaves with the PVR setting, causing an unexpected bug in KVM-HV migrations between hosts that are compatible (POWER8 and POWER8E, for example). Even with pvr_match() returning true, the guest freezes right after cpu_post_load. The reason is that the guest kernel can't handle a different PVR value other that the running host in KVM_SET_SREGS. In [1] it was discussed the possibility of a new KVM capability that would indicate that the guest kernel can handle a different PVR in KVM_SET_SREGS. Even if such feature is implemented, there is still the problem with older kernels that will not have this capability and will fail to migrate. This patch implements a workaround for that scenario. If running with KVM, check if the guest kernel does not have the capability (named here as 'cap_ppc_pvr_compat'). If it doesn't, calls kvmppc_is_pr() to see if the guest is running in KVM-HV. If all this happens, set env->spr[SPR_PVR] to the same value as the current host PVR. This ensures that we allow migrations with 'close enough' PVRs to still work in KVM-HV but also makes the code ready for this new KVM capability when it is done. A new function called 'kvmppc_pvr_workaround_required' was created to encapsulate the conditions said above and to avoid calling too many kvm.c internals inside cpu_post_load. [1] https://lists.gnu.org/archive/html/qemu-ppc/2017-06/msg00503.html Signed-off-by: Daniel Henrique Barboza <danielhb@linux.vnet.ibm.com> [dwg: Fix for the case of using TCG on a PPC host] Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
* target/arm: Require alignment for load exclusiveAlistair Francis2017-08-151-5/+6
| | | | | | | | | | | | | | According to the ARM ARM exclusive loads require the same alignment as exclusive stores. Let's update the memops used for the load to match that of the store. This adds the alignment requirement to the memops. Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20170815145714.17635-4-richard.henderson@linaro.org [rth: Require 16-byte alignment for 64-bit LDXP.] Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target/arm: Correct load exclusive pair atomicityRichard Henderson2017-08-151-23/+37
| | | | | | | | | | | | | | | | | | We are not providing the required single-copy atomic semantics for the 64-bit operation that is the 32-bit paired load. At the same time, leave the entire 64-bit value in cpu_exclusive_val and stop writing to cpu_exclusive_high. This means that we do not have to re-assemble the 64-bit quantity when it comes time to store. At the same time, drop a redundant temporary and perform all loads directly into the cpu_exclusive_* globals. Tested-by: Alistair Francis <alistair.francis@xilinx.com> Reviewed-by: Alistair Francis <alistair.francis@xilinx.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20170815145714.17635-3-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target/arm: Correct exclusive store cmpxchg memop maskAlistair Francis2017-08-151-1/+1
| | | | | | | | | | | | | | | | | | When we perform the atomic_cmpxchg operation we want to perform the operation on a pair of 32-bit registers. Previously we were just passing the register size in which was set to MO_32. This would result in the high register to be ignored. To fix this issue we hardcode the size to be 64-bits long when operating on 32-bit pairs. Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Tested-by: Portia Stephens <portia.stephens@xilinx.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20170815145714.17635-2-richard.henderson@linaro.org Message-Id: <bc18dddca56e8c2ea4a3def48d33ceb5d21d1fff.1502488636.git.alistair.francis@xilinx.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* unicore32: abort when entering "x 0" on the monitorEduardo Otubo2017-08-141-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | Starting Qemu with "qemu-system-unicore32 -M puv3,accel=qtest -S -nographic" and entering "x 0 " at the monitor prompt leads to abort(): $ ./unicore32-softmmu/qemu-system-unicore32 -M puv3,accel=qtest -S -nographic QEMU 2.9.90 monitor - type 'help' for more information (qemu) x 0 qemu: fatal: uc32_cpu_get_phys_page_debug not supported yet R00=00000000 R01=00000000 R02=00000000 R03=00000000 R04=00000000 R05=00000000 R06=00000000 R07=00000000 R08=00000000 R09=00000000 R10=00000000 R11=00000000 R12=00000000 R13=00000000 R14=00000000 R15=00000000 R16=00000000 R17=00000000 R18=00000000 R19=00000000 R20=00000000 R21=00000000 R22=00000000 R23=00000000 R24=00000000 R25=00000000 R26=00000000 R27=00000000 R28=00000000 R29=00000000 R30=00000000 R31=03000000 PSR=40000013 -Z-- PRIV Aborted (core dumped) This happens because uc32_cpu_get_phys_page_debug() is not implemented yet, this is a temporary workaround to avoid the crash. Signed-off-by: Eduardo Otubo <otubo@redhat.com> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
* target/ppc: Add stub implementation of the PSSCRDavid Gibson2017-08-092-0/+6
| | | | | | | | | | | | | | | | | | The PSSCR register added in POWER9 controls certain power saving mode behaviours. Mostly, it's not relevant to TCG, however because qemu doesn't know about it yet, it doesn't synchronize the state with KVM, and thus it doesn't get migrated. To fix that, this adds a minimal stub implementation of the register. This isn't complete, even to the extent that an implementation is possible in TCG, just enough to get migration working. We need to come back later and at least properly filter the various fields in the register based on privilege level. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Reviewed-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Greg Kurz <groug@kaod.org> Reviewed-by: Thomas Huth <thuth@redhat.com>
* target/ppc: Implement TIDRDavid Gibson2017-08-092-0/+6
| | | | | | | | | | | | | | This adds a trivial implementation of the TIDR register added in POWER9. This isn't particularly important to qemu directly - it's used by accelerator modules that we don't emulate. However, since qemu isn't aware of it, its state is not synchronized with KVM and therefore not migrated, which can be a problem. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Reviewed-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Greg Kurz <groug@kaod.org> Reviewed-by: Thomas Huth <thuth@redhat.com>
* ppc: fix double-free in cpu_post_load()Greg Kurz2017-08-091-1/+0Star
| | | | | | | | | | | When running nested with KVM PR, ppc_set_compat() fails and QEMU crashes because of "double free or corruption (!prev)". The crash happens because error_report_err() has already called error_free(). Signed-off-by: Greg Kurz <groug@kaod.org> Reviewed-by: Eric Blake <eblake@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
* booke206: fix MAS update on tlb missKONRAD Frederic2017-08-091-1/+1
| | | | | | | | | | | When a tlb instruction miss happen, rw is set to 0 at the bottom of cpu_ppc_handle_mmu_fault which cause the MAS update function to miss the SAS and TS bit in MAS6, MAS1 in booke206_update_mas_tlb_miss. Just calling booke206_update_mas_tlb_miss with rw = 2 solve the issue. Signed-off-by: KONRAD Frederic <frederic.konrad@adacore.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
* Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into stagingPeter Maydell2017-08-081-0/+1
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * --help/--version improvements (Eric) * GCC 7 workaround (Greg) * Small SCSI fix (Hannes) * SSE 4.1 fix (Joseph) * RCU deadlock fix (myself) # gpg: Signature made Tue 08 Aug 2017 16:28:56 BST # gpg: using RSA key 0xBFFBD25F78C7AE83 # gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" # gpg: aka "Paolo Bonzini <pbonzini@redhat.com>" # Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4 E2F7 7E15 100C CD36 69B1 # Subkey fingerprint: F133 3857 4B66 2389 866C 7682 BFFB D25F 78C7 AE83 * remotes/bonzini/tags/for-upstream: maint: Include bug-reporting info in --help output qga: Give more --version information qemu-io: Give more --version information qemu-img: Sort sub-command names in --help target/i386: set rip_offset for some SSE4.1 instructions scsi: clarify sense codes for LUN0 emulation kvm: workaround build break on gcc-7.1.1 / fedora26 Revert "rcu: do not create thread in pthread_atfork callback" rcu: completely disable pthread_atfork callbacks as soon as possible Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * target/i386: set rip_offset for some SSE4.1 instructionsJoseph Myers2017-08-081-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When emulating various SSE4.1 instructions such as pinsrd, the address of a memory operand is computed without allowing for the 8-bit immediate operand located after the memory operand, meaning that the memory operand uses the wrong address in the case where it is rip-relative. This patch adds the required rip_offset setting for those instructions, so fixing some GCC test failures (13 in the gcc testsuite in my GCC 6-based testing) when testing with a default CPU setting enabling those instructions. Signed-off-by: Joseph Myers <joseph@codesourcery.com> Message-Id: <alpine.DEB.2.20.1708080041391.28702@digraph.polyomino.org.uk> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* | Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20170803' into stagingPeter Maydell2017-08-041-0/+1
|\ \ | |/ |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Queued misc tcg patches # gpg: Signature made Thu 03 Aug 2017 19:07:18 BST # gpg: using RSA key 0xAD1270CC4DD0279B # gpg: Good signature from "Richard Henderson <rth7680@gmail.com>" # gpg: aka "Richard Henderson <rth@twiddle.net>" # Primary key fingerprint: 9CB1 8DDA F8E8 49AD 2AFC 16A4 AD12 70CC 4DD0 279B * remotes/rth/tags/pull-tcg-20170803: tcg: Increase minimum alignment from tcg_malloc to 8 target/s390x: Fix CSST for 16-byte store tcg/arm: Fix runtime overalignment test Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * target/s390x: Fix CSST for 16-byte storeRichard Henderson2017-08-031-0/+1
| | | | | | | | | | | | | | | | Found by Coverity (CID 1378273). Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reported-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Richard Henderson <rth@twiddle.net>
* | target/mips: Fix RDHWR CC with icountJames Hogan2017-08-021-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | RDHWR CC reads the CPU timer like MFC0 CP0_Count, so with icount enabled it must set can_do_io while it calls the helper to avoid the "Bad icount read" error. It should also break out of the translation loop to ensure that timer interrupts are immediately handled. Fixes: 2e70f6efa8b9 ("Add instruction counter.") Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Aurelien Jarno <aurelien@aurel32.net> Cc: Yongbok Kim <yongbok.kim@imgtec.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com>
* | target/mips: Drop redundant gen_io_start/stop()James Hogan2017-08-021-8/+0Star
| | | | | | | | | | | | | | | | | | | | | | | | | | DMTC0 CP0_Cause does a redundant gen_io_start() and gen_io_end() pair, even though this is done for all DMTC0 operations outside of the switch statement. Remove these redundant calls. Fixes: 5dc5d9f055c5 ("mips: more fixes to the MIPS interrupt glue logic") Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Yongbok Kim <yongbok.kim@imgtec.com> Cc: Aurelien Jarno <aurelien@aurel32.net> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com>
* | target/mips: Use BS_EXCP where interrupts are expectedJames Hogan2017-08-021-13/+34
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit e350d8ca3ac7 ("target/mips: optimize indirect branches") made indirect branches able to directly find the next TB and jump straight to it without breaking out of translated code and going around the main execution loop. This breaks the assumption in target/mips/translate.c that BS_STOP is sufficient to cause pending interrupts to be handled, since interrupts are only checked in the main loop. Fix a few of these assumptions by using gen_save_pc to update the saved PC and using BS_EXCP instead of BS_STOP: - [D]MFC0 CP0_Count may trigger a timer interrupt which should be immediately handled. - [D]MTC0 CP0_Cause may trigger an interrupt (but in fact translation was only even being stopped in the DMTC0 case). - [D]MTC0 CP0_<any> when icount is used is assumed could potentially cause interrupts. - EI may trigger an interrupt which was pending. I specifically hit this case when running KVM nested in mipsel-softmmu. A timer interrupt while the 2nd guest was executing is caught by KVM which switches back to the normal Linux exception base and re-enables interrupts with EI. Since the above commit QEMU doesn't leave translated code until the nested KVM has already restored the KVM exception base and returned to the 2nd guest, at which point it is too late to check for pending interrupts and it gets stuck in an infinite loop of unhandled interrupts. Something similar was needed for ARM in commit b29fd33db578 ("target/arm: use DISAS_EXIT for eret handling"). Fixes: e350d8ca3ac7 ("target/mips: optimize indirect branches") Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Aurelien Jarno <aurelien@aurel32.net> Cc: Yongbok Kim <yongbok.kim@imgtec.com> Cc: Richard Henderson <rth@twiddle.net> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com>
* | target-mips: apply CP0.PageMask before writing into TLB entryLeon Alrae2017-08-021-2/+3
| | | | | | | | | | | | | | | | | | | | PFN0 and PFN1 have to be masked out with PageMask_Mask. Signed-off-by: Leon Alrae <leon.alrae@imgtec.com> Reviewed-by: Yongbok Kim <yongbok.kim@imgtec.com> [Yongbok Kim: Added commit message] Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com>
* | mips: Add KVM T&E segment support for TCGJames Hogan2017-08-022-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | MIPS KVM trap & emulate guest kernels have a different segment layout compared with traditional MIPS kernels, to allow both the user and kernel code to run from the user address segment without repeatedly trapping to KVM. QEMU currently supports this layout only for KVM, but its sometimes useful to be able to run these kernels in QEMU on a PC, so enable it for TCG too. This also paves the way for MIPS KVM VZ support (which uses the normal virtual memory layout) by abstracting whether user mode kernel segments are in use. Suggested-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Yongbok Kim <yongbok.kim@imgtec.com> Cc: Aurelien Jarno <aurelien@aurel32.net> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: kvm@vger.kernel.org Reviewed-by: Richard Henderson <rth@twiddle.net> [Yongbok Kim: minor change] Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com>
* | mips: Improve segment defs for KVM T&E guestsJames Hogan2017-08-021-12/+11Star
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Improve the segment definitions used by get_physical_address() to yield target_ulong types, e.g. 0xffffffff80000000 instead of 0x80000000. This is in preparation for enabling emulation of MIPS KVM T&E segments in TCG MIPS targets, which unlike KVM could potentially have 64-bit target_ulong. In such a case the offset guest KSEG0 address ends up at e.g. 0x000000008xxxxxxx instead of 0xffffffff8xxxxxxx. This also allows the casts to int32_t that force sign extension to be removed, which removes any confusion due to relational comparison of unsigned (target_ulong) and signed (int32_t) types. Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Yongbok Kim <yongbok.kim@imgtec.com> Cc: Aurelien Jarno <aurelien@aurel32.net> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: kvm@vger.kernel.org Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com>
* | target-mips: Don't stop on [d]mtc0 DESAVE/KScratchJames Hogan2017-08-021-4/+0Star
|/ | | | | | | | | | | | | | | | | Writing to the MIPS DESAVE register (and now the KScratch registers) will stop translation, supposedly due to risk of execution mode switches. However these registers are basically RW scratch registers with no side effects so there is no risk of them triggering execution mode changes. Drop the bstate = BS_STOP for these registers for both mtc0 and dmtc0. Fixes: 7a387fffce50 ("Add MIPS32R2 instructions, and generally straighten out the instruction decoding. This is also the first percent towards MIPS64 support.") Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Aurelien Jarno <aurelien@aurel32.net> Cc: Yongbok Kim <yongbok.kim@imgtec.com> Reviewed-by: Yongbok Kim <yongbok.kim@imgtec.com> Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com>
* target-i386: kvm_get/put_vcpu_events don't handle sipi_vectorPeng Hao2017-08-011-15/+20
| | | | | | | | | | | | qemu call kvm_get_vcpu_events, and kernel return sipi_vector always 0, never valid when reporting to user space. But when qemu calls kvm_put_vcpu_events will make sipi_vector in kernel be 0. This will accidently modify sipi_vector when sipi_vector in kernel is not 0. Signed-off-by: Peng Hao <peng.hao2@zte.com.cn> Reviewed-by: Liu Yi <liu.yi24@zte.com.cn> Message-Id: <1500047256-8911-1-git-send-email-peng.hao2@zte.com.cn> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* trace-events: fix code style: print 0x before hex numbersVladimir Sementsov-Ogievskiy2017-08-013-21/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The only exception are groups of numers separated by symbols '.', ' ', ':', '/', like 'ab.09.7d'. This patch is made by the following: > find . -name trace-events | xargs python script.py where script.py is the following python script: ========================= #!/usr/bin/env python import sys import re import fileinput rhex = '%[-+ *.0-9]*(?:[hljztL]|ll|hh)?(?:x|X|"\s*PRI[xX][^"]*"?)' rgroup = re.compile('((?:' + rhex + '[.:/ ])+' + rhex + ')') rbad = re.compile('(?<!0x)' + rhex) files = sys.argv[1:] for fname in files: for line in fileinput.input(fname, inplace=True): arr = re.split(rgroup, line) for i in range(0, len(arr), 2): arr[i] = re.sub(rbad, '0x\g<0>', arr[i]) sys.stdout.write(''.join(arr)) ========================= Signed-off-by: Vladimir Sementsov-Ogievskiy <vsementsov@virtuozzo.com> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Acked-by: Cornelia Huck <cohuck@redhat.com> Message-id: 20170731160135.12101-5-vsementsov@virtuozzo.com Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
* target/arm: Migrate MPU_RNR register state for M profile coresPeter Maydell2017-07-311-0/+28
| | | | | | | | | | | | The PMSAv7 region number register is migrated for R profile cores using the cpreg scheme, but M profile doesn't use cpregs, and so we weren't migrating the MPU_RNR register state at all. Fix that by adding a migration subsection for the M profile case. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 1501153150-19984-6-git-send-email-peter.maydell@linaro.org
* target/arm: Move PMSAv7 reset into arm_cpu_reset() so M profile MPUs get resetPeter Maydell2017-07-312-16/+26
| | | | | | | | | | | | When the PMSAv7 implementation was originally added it was for R profile CPUs only, and reset was handled using the cpreg .resetfn hooks. Unfortunately for M profile cores this doesn't work, because they do not register any cpregs. Move the reset handling into arm_cpu_reset(), where it will work for both R profile and M profile cores. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 1501153150-19984-5-git-send-email-peter.maydell@linaro.org
* target/arm: Rename cp15.c6_rgnr to pmsav7.rnrPeter Maydell2017-07-313-6/+5Star
| | | | | | | | | | | | | | Almost all of the PMSAv7 state is in the pmsav7 substruct of the ARM CPU state structure. The exception is the region number register, which is in cp15.c6_rgnr. This exception is a bit odd for M profile, which otherwise generally does not store state in the cp15 substruct. Rename cp15.c6_rgnr to pmsav7.rnr accordingly. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 1501153150-19984-4-git-send-email-peter.maydell@linaro.org
* target/arm: Don't allow guest to make System space executable for M profilePeter Maydell2017-07-311-1/+15
| | | | | | | | | | For an M profile v7PMSA, the system space (0xe0000000 - 0xffffffff) can never be executable, even if the guest tries to set the MPU registers up that way. Enforce this restriction. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 1501153150-19984-3-git-send-email-peter.maydell@linaro.org
* target/arm: Don't do MPU lookups for addresses in M profile PPB regionPeter Maydell2017-07-311-1/+16
| | | | | | | | | | | | The M profile PMSAv7 specification says that if the address being looked up is in the PPB region (0xe0000000 - 0xe00fffff) then we do not use the MPU regions but always use the default memory map. Implement this (we were previously behaving like an R profile PMSAv7, which does not special case this). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 1501153150-19984-2-git-send-email-peter.maydell@linaro.org
* target/arm: Correct MPU trace handling of write vs executePeter Maydell2017-07-311-2/+2
| | | | | | | | | | | | | Correct off-by-one bug in the PSMAv7 MPU tracing where it would print a write access as "reading", an insn fetch as "writing", and a read access as "execute". Since we have an MMUAccessType enum now, we can make the code clearer in the process by using that rather than the raw 0/1/2 values. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Message-id: 1500906792-18010-1-git-send-email-peter.maydell@linaro.org
* docs: fix broken paths to docs/devel/tracing.txtPhilippe Mathieu-Daudé2017-07-316-6/+6
| | | | | | | | | With the move of some docs/ to docs/devel/ on ac06724a71, no references were updated. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
generated by cgit v1.2.3-55-g7522 (git 2.39.0) at 2024-12-22 17:38:24 +0100